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| author |   Shawn Guo <shawn.guo@linaro.org> | 2021-03-26 19:02:14 +0800 |
|---|---|---|
| committer |   Ulf Hansson <ulf.hansson@linaro.org> | 2021-03-30 12:42:54 +0200 |
| commit | 25e8b9eb096d057bd5c8095d6a95c16091331e82 (patch) | |
| tree | ad949d4e30be0f1a399f84f6fe60274a9922a986 /mm | |
| parent | mmc: sdhci-brcmstb: Remove CQE quirk (diff) | |
| download | linux-dev-25e8b9eb096d057bd5c8095d6a95c16091331e82.tar.xz linux-dev-25e8b9eb096d057bd5c8095d6a95c16091331e82.zip | |
mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check
As indicated by function esdhc_change_pinstate(), SDR50 and DDR50
require pins_100mhz, while SDR104 and HS400 require pins_200mhz. Some
system design may support SDR50 and DDR50 with 100mhz pin state only
(without 200mhz one). Currently the combined 100/200 MHz pinctrl state
check prevents such system from running SDR50 and DDR50. Separate the
check to support such system design.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://lore.kernel.org/r/20210326110214.28416-1-shawnguo@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'mm')
0 files changed, 0 insertions, 0 deletions