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| author |   Yazen Ghannam <yazen.ghannam@amd.com> | 2019-08-21 23:59:57 +0000 |
|---|---|---|
| committer |   Borislav Petkov <bp@suse.de> | 2019-08-23 07:06:29 +0200 |
| commit | 353a1fcb8f9e5857c0fb720b9e57a86c1fb7c17e (patch) | |
| tree | f4840cefffa8a6aa9737bd4fed1ed91fb4281669 /net | |
| parent | EDAC/amd64: Recognize DRAM device type ECC capability (diff) | |
| download | linux-dev-353a1fcb8f9e5857c0fb720b9e57a86c1fb7c17e.tar.xz linux-dev-353a1fcb8f9e5857c0fb720b9e57a86c1fb7c17e.zip | |
EDAC/amd64: Initialize DIMM info for systems with more than two channels
Currently, the DIMM info for AMD Family 17h systems is initialized in
init_csrows(). This function is shared with legacy systems, and it has a
limit of two channel support.
This prevents initialization of the DIMM info for a number of ranks, so
there will be missing ranks in the EDAC sysfs.
Create a new init_csrows_df() for Family17h+ and revert init_csrows()
back to pre-Family17h support.
Loop over all channels in the new function in order to support systems
with more than two channels.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Tony Luck <tony.luck@intel.com>
Link: https://lkml.kernel.org/r/20190821235938.118710-4-Yazen.Ghannam@amd.com
Diffstat (limited to 'net')
0 files changed, 0 insertions, 0 deletions