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| author |   Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-08-25 00:06:26 +0200 |
|---|---|---|
| committer |   Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-07 17:03:56 +0100 |
| commit | 900c33e86e4b53e96e6ea10e9737870e03911a66 (patch) | |
| tree | 8dff709510edc0705b6368f05058a6fccf46cf94 /samples/git:/ssh:/git@git.zx2c4.com | |
| parent | media: ccs: Dual PLL support (diff) | |
| download | linux-dev-900c33e86e4b53e96e6ea10e9737870e03911a66.tar.xz linux-dev-900c33e86e4b53e96e6ea10e9737870e03911a66.zip | |
media: ccs-pll: Add support for DDR OP system and pixel clocks
Add support for dual data rate operational system and pixel clocks. This
is implemented using two PLL flags.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'samples/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions