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| author |   Aapo Vienamo <avienamo@nvidia.com> | 2018-08-10 21:08:08 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2018-08-27 12:25:17 +0200 |
| commit | 00ead3c913afe8872a428e56e2a815adb2b230d1 (patch) | |
| tree | d5156cc9193871b9c37d2d6a0fe6ecd80f3e60f0 /samples/hidraw/ssh:/git@git.zx2c4.com/git: | |
| parent | soc/tegra: pmc: Fix pad voltage configuration for Tegra186 (diff) | |
soc/tegra: pmc: Factor out DPD register bit calculation
Factor out the the code to calculate the correct DPD register and bit
number for a given pad. This logic will be needed to query the status
register.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'samples/hidraw/ssh:/git@git.zx2c4.com/git:')
0 files changed, 0 insertions, 0 deletions