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authorGustavo A. R. Silva <garsilva@embeddedor.com>2018-01-15 13:15:28 -0600
committerMichal Simek <michal.simek@xilinx.com>2018-01-16 15:50:20 +0100
commit2a7157b137f6f4804fbd60e8734574373212105b (patch)
treeeac53f0c9cee9a753fce61ff7837242d93f26a10 /samples/hidraw/ssh:/git@git.zx2c4.com/git:
parentsoc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcu (diff)
soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv
Currently clkoutdiv is being operated on by a logical && operator rather than a bitwise & operator. This looks incorrect as these should be bit flag operations. Addresses-Coverity-ID: 1463959 ("Logical vs. bitwise operator") Fixes: cee8113a295a ("soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver") Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Acked-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'samples/hidraw/ssh:/git@git.zx2c4.com/git:')
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