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authorHeiko Stuebner <heiko@sntech.de>2018-11-15 12:17:30 +0100
committerHeiko Stuebner <heiko@sntech.de>2018-11-15 12:19:09 +0100
commitac8cb53829a6ba119082e067f5bc8fab3611ce6a (patch)
tree69bf639c40dcac0b97729b4935f82780bee04803 /samples/hidraw/ssh:/git@git.zx2c4.com/git:
parentclk: rockchip: fix rk3188 sclk_smc gate data (diff)
clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering
Similar to commit a9f0c0e56371 ("clk: rockchip: fix rk3188 sclk_smc gate data") there is one other gate clock in the rk3188 clock driver with a similar wrong ordering, the sclk_mac_lbtest. So fix it as well. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'samples/hidraw/ssh:/git@git.zx2c4.com/git:')
0 files changed, 0 insertions, 0 deletions