diff options
| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-10 11:46:10 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-21 11:12:23 +0100 |
| commit | cecbe87d73006cb321dec79b349e3fefd1a80962 (patch) | |
| tree | 70063577f87854f64623c482b7227ee3734810c2 /scripts/Makefile.headersinst | |
| parent | clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init() (diff) | |
clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0
Add a workaround for errata on R-Car H3 ES1.0, where the PLL0, PLL2, and
PLL4 clock frequencies are off by a factor of two.
Inspired by a patch by Dien Pham in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Dien Pham <dien.pham.ry@renesas.com>
Diffstat (limited to 'scripts/Makefile.headersinst')
0 files changed, 0 insertions, 0 deletions