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| author | 2017-02-28 17:31:59 +0100 | |
|---|---|---|
| committer | 2017-03-21 11:12:07 +0100 | |
| commit | a843ed3f6c3e856f9091b042c6b4ed34c02a3187 (patch) | |
| tree | 7b7b0817c3d5143aff696a3c11fad97b645a5cb6 /scripts/basic | |
| parent | clk: renesas: r8a7796: Add IMR clocks (diff) | |
clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs
The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which
maps to S3D1 on R-Car H3 ES1.x.
All module clocks must be sorted by clock ID.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Diffstat (limited to 'scripts/basic')
0 files changed, 0 insertions, 0 deletions
