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| author | 2017-08-01 21:13:24 -0400 | |
|---|---|---|
| committer | 2017-09-26 18:16:16 -0400 | |
| commit | 0d18d7bb80132467a3b88a2fe7277dc1fee65353 (patch) | |
| tree | c3b3b457067aeedecfeb3e0e88dfdad6b877a2b2 /scripts/checkstack.pl | |
| parent | drm/amd/display: update predefined latency for Rv1_F0 (diff) | |
drm/amd/display: fix dlg ttu calculation input
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/checkstack.pl')
0 files changed, 0 insertions, 0 deletions
