diff options
| author |   Bruce Allan <bruce.w.allan@intel.com> | 2010-11-24 06:01:41 +0000 |
|---|---|---|
| committer |   Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2010-12-10 22:13:27 -0800 |
| commit | ce54afd16d874ac07378a8bb55d26f7f5b613c0e (patch) | |
| tree | abad7c3150c4acbf3012168d71d611523459694a /scripts/const_structs.checkpatch | |
| parent | e1000e: 82571 Serdes can fail to get link (diff) | |
e1000e: 82577/8/9 mis-configured OEM bits during S0->Sx
The LPLU (Low Power Link Up) and Gigabit Disable bits (a.k.a. OEM bits)
were being configured incorrectly when device goes to D3 state.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'scripts/const_structs.checkpatch')
0 files changed, 0 insertions, 0 deletions