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| author |   Eric Yang <Eric.Yang2@amd.com> | 2017-07-05 15:30:18 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:08:40 -0400 |
| commit | 133e8e1b35c7772f4903d367035e33e02becbb2d (patch) | |
| tree | 3432bb467aa5d2d510d50f9d8e58eb932257bd4e /scripts/diffconfig | |
| parent | drm/amd/display: block modes that require read bw greater than 30% (diff) | |
drm/amd/display: Change how we disable pipe split
Before this change, pipe split was disabled by bumping up dpp clock
bounding box for DPM level 0 and 1, this allows validation to pass
without splitting at a lower DPM level. This change reverts this
and instead lowers display clock at DPM level 0, this forces
configurations that need pipe split at DPM level 0 to go to
DPM level 1, where they can be driven without split.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/diffconfig')
0 files changed, 0 insertions, 0 deletions