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| author |   Marc Zyngier <maz@kernel.org> | 2022-04-05 19:23:26 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-05-04 14:09:53 +0100 |
| commit | 4645d11f4a5538ec1221f36e397cfb0115718ffe (patch) | |
| tree | 6ad52be9cbdd181135c5a4b2baa5af4bbd7425d6 /scripts/gdb/linux/utils.py | |
| parent | KVM: arm64: vgic-v3: Expose GICR_CTLR.RWP when disabling LPIs (diff) | |
| download | linux-dev-4645d11f4a5538ec1221f36e397cfb0115718ffe.tar.xz linux-dev-4645d11f4a5538ec1221f36e397cfb0115718ffe.zip | |
KVM: arm64: vgic-v3: Implement MMIO-based LPI invalidation
Since GICv4.1, it has become legal for an implementation to advertise
GICR_{INVLPIR,INVALLR,SYNCR} while having an ITS, allowing for a more
efficient invalidation scheme (no guest command queue contention when
multiple CPUs are generating invalidations).
Provide the invalidation registers as a primitive to their ITS
counterpart. Note that we don't advertise them to the guest yet
(the architecture allows an implementation to do this).
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Oliver Upton <oupton@google.com>
Link: https://lore.kernel.org/r/20220405182327.205520-4-maz@kernel.org
Diffstat (limited to 'scripts/gdb/linux/utils.py')
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