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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-08 15:41:10 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-13 11:53:18 +0200 |
| commit | 65d012e415bb3592cd1c492195ff19088166198b (patch) | |
| tree | c83b99bcb75cb89bc59db2d2c816b4d9de9607e2 /scripts/gdb/linux/utils.py | |
| parent | clk: renesas: r8a779f0: Add SDHI0 clock (diff) | |
| download | linux-dev-65d012e415bb3592cd1c492195ff19088166198b.tar.xz linux-dev-65d012e415bb3592cd1c492195ff19088166198b.zip | |
clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg
The register block base pointer as stored in the reg member of the
r8a73a4_cpg structure is only used during initialization. Hence move
it to a local variable, and pass it as a parameter to
r8a73a4_cpg_register_clock().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f835f3dfcf3bf754065e5002663952cc6341caac.1654694831.git.geert+renesas@glider.be
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions