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| author |   Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2019-05-17 09:36:25 +0530 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2019-05-20 01:00:32 +0200 |
| commit | 0ee198ab08fe1b7cca93a81ad658954534963cb0 (patch) | |
| tree | 4d0c58b774e45a658f2defb6e2b50731538f18c8 /scripts/gen_compile_commands.py | |
| parent | arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960 (diff) | |
| download | linux-dev-0ee198ab08fe1b7cca93a81ad658954534963cb0.tar.xz linux-dev-0ee198ab08fe1b7cca93a81ad658954534963cb0.zip | |
arm64: dts: rockchip: Enable SPI1 on Ficus
Enable SPI1 exposed on both Low and High speed expansion connectors
of Ficus. SPI1 has 3 different chip selects wired as below:
CS0 - Serial Flash (unpopulated)
CS1 - Low Speed expansion
CS2 - High Speed expansion
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'scripts/gen_compile_commands.py')
0 files changed, 0 insertions, 0 deletions