diff options
| author |   Catalin Marinas <catalin.marinas@arm.com> | 2009-05-30 14:00:16 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2009-05-30 14:00:16 +0100 |
| commit | 23d1c515d8fc6d74bea442a4b687c3b5b8627ec4 (patch) | |
| tree | d257dedacef94e47006d7daca00e698296e9fa38 /scripts/patch-kernel | |
| parent | ARMv7: Enable the SWP instruction (diff) | |
ARMv7: Document the PRRR and NMRR registers setting
This patch adds a comment to the proc-v7.S file for the setting of the
PRRR and NMRR registers. It also sets the PRRR[13:12] bits to 0
(corresponding to the reserved TEX[0]CB encoding 110) to be consistent
with the documentation.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'scripts/patch-kernel')
0 files changed, 0 insertions, 0 deletions