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| author |   Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-09-01 15:04:57 +0200 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2018-09-26 16:50:38 +0200 |
| commit | e0cffa9a1b64099f537887712ba3802f92429675 (patch) | |
| tree | 11a0b1aef873a965d1d0f919a65ce5944bae4c8b /scripts/stackusage | |
| parent | ARM: tegra: apalis-tk1: add toradex, apalis-tk1-v1.2 compatible (diff) | |
ARM: tegra: apalis-tk1: reorder cpu dfll clock properties
Reorder CPU DFLL clock properties.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'scripts/stackusage')
0 files changed, 0 insertions, 0 deletions