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| author | 2022-06-07 10:35:39 -0700 | |
|---|---|---|
| committer | 2022-07-21 17:19:25 -0700 | |
| commit | 7f8faf96a2fb562833db73595640329ca8da7b1d (patch) | |
| tree | aa1d56a296dd10cf81a951324fe07594e9773722 /scripts | |
| parent | cxl/hdm: Add sysfs attributes for interleave ways + granularity (diff) | |
| download | linux-dev-7f8faf96a2fb562833db73595640329ca8da7b1d.tar.xz linux-dev-7f8faf96a2fb562833db73595640329ca8da7b1d.zip | |
cxl/mem: Enumerate port targets before adding endpoints
The port scanning algorithm in devm_cxl_enumerate_ports() walks up the
topology and adds cxl_port objects starting from the root down to the
endpoint. When those ports are initially created they know all their
dports, but they do not know the downstream cxl_port instance that
represents the next descendant in the topology. Rework create_endpoint()
into devm_cxl_add_endpoint() that enumerates the downstream cxl_port
topology into each port's 'struct cxl_ep' record for each endpoint it
that the port is an ancestor.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20220624041950.559155-7-dan.j.williams@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions
