aboutsummaryrefslogtreecommitdiffstats
path: root/sound/pci
diff options
context:
space:
mode:
authorLibin Yang <libin.yang@intel.com>2015-04-07 20:32:20 +0800
committerTakashi Iwai <tiwai@suse.de>2015-04-07 14:51:35 +0200
commit2d846c74027231264e57e4e34faf9576394e3ce0 (patch)
tree7c4da62bace11e6a44ef268fa1d8c9ab29ac890a /sound/pci
parentALSA: emu10k1: add Audigy 5/Rx (diff)
downloadlinux-dev-2d846c74027231264e57e4e34faf9576394e3ce0.tar.xz
linux-dev-2d846c74027231264e57e4e34faf9576394e3ce0.zip
ALSA: hda_intel: add AZX_DCAPS_I915_POWERWELL for SKL and BSW
HDMI/DP codec on SKL/BSW is in the power well. The power well must be turned on before probing the HDMI/DP codec. This is a temporary patch, which will power on the powerwell by adding AZX_DCAPS_I915_POWERWELL for SKL and BSW. After restructuring and new flag is added, this patch will be reverted. Signed-off-by: Libin Yang <libin.yang@intel.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/pci')
-rw-r--r--sound/pci/hda/hda_intel.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index feebc1dda912..9bcc5457a83e 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -297,8 +297,12 @@ enum {
AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
AZX_DCAPS_SNOOP_TYPE(SCH))
+#define AZX_DCAPS_INTEL_BRASWELL \
+ (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
+
#define AZX_DCAPS_INTEL_SKYLAKE \
- (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG)
+ (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
+ AZX_DCAPS_I915_POWERWELL)
/* quirks for ATI SB / AMD Hudson */
#define AZX_DCAPS_PRESET_ATI_SB \
@@ -1991,7 +1995,7 @@ static const struct pci_device_id azx_ids[] = {
.driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
/* Braswell */
{ PCI_DEVICE(0x8086, 0x2284),
- .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
+ .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
/* ICH6 */
{ PCI_DEVICE(0x8086, 0x2668),
.driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },