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| author |   Takashi Iwai <tiwai@suse.de> | 2018-06-05 16:51:55 +0200 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2018-06-05 16:51:55 +0200 |
| commit | d4d5a1cd298e67cb68cca8dc7dd1ea3942cce3ff (patch) | |
| tree | 282417771a28cb3d88fdd3246d9b778f1e3e8fd3 /sound/soc/codecs | |
| parent | ALSA: usb-audio: remove redundant check on err (diff) | |
| parent | Merge branch 'asoc-4.17' into asoc-4.18 merge window (diff) | |
| download | linux-dev-d4d5a1cd298e67cb68cca8dc7dd1ea3942cce3ff.tar.xz linux-dev-d4d5a1cd298e67cb68cca8dc7dd1ea3942cce3ff.zip | |
Merge tag 'asoc-v4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
ASoC: Updates for v4.18
This is a very big update, mainly due to a huge set of new drivers some
of which are individually very large. We also have a lot of fixes for
the topology stuff, several of the users have stepped up and fixed some
the serious issues there, and continued progress on the transition away
from CODEC specific drivers to generic component drivers.
- Many fixes for the topology code, including fixes for the half done
v4 ABI compatibility from Guenter Roeck and other ABI fixes from
Kirill Marinushkin.
- Lots of cleanup for Intel platforms based on Realtek CODECs from Hans
de Goode.
- More followups on removing legacy CODEC things and transitioning to
components from Morimoto-san.
- Conversion of OMAP DMA to the new, more standard SDMA-PCM driver.
- A series of fixes and updates to the rather elderly Cirrus Logic SoC
drivers from Alexander Sverdlin.
- Qualcomm DSP support from Srinivas Kandagatla.
- New drivers for Analog SSM2305, Atmel I2S controllers, Mediatek
MT6351, MT6797 and MT7622, Qualcomm DSPs, Realtek RT1305, RT1306 and
RT5668 and TI TSCS454
Diffstat (limited to 'sound/soc/codecs')
41 files changed, 13915 insertions, 311 deletions
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 9548f63ca531..63cf62e9c9aa 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -106,6 +106,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_MAX9877 if I2C select SND_SOC_MC13783 if MFD_MC13XXX select SND_SOC_ML26124 if I2C + select SND_SOC_MT6351 if MTK_PMIC_WRAP select SND_SOC_NAU8540 if I2C select SND_SOC_NAU8810 if I2C select SND_SOC_NAU8824 if I2C @@ -126,6 +127,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_RT274 if I2C select SND_SOC_RT286 if I2C select SND_SOC_RT298 if I2C + select SND_SOC_RT1305 if I2C select SND_SOC_RT5514 if I2C select SND_SOC_RT5616 if I2C select SND_SOC_RT5631 if I2C @@ -136,12 +138,14 @@ config SND_SOC_ALL_CODECS select SND_SOC_RT5660 if I2C select SND_SOC_RT5663 if I2C select SND_SOC_RT5665 if I2C + select SND_SOC_RT5668 if I2C select SND_SOC_RT5670 if I2C select SND_SOC_RT5677 if I2C && SPI_MASTER select SND_SOC_SGTL5000 if I2C select SND_SOC_SI476X if MFD_SI476X_CORE select SND_SOC_SIRF_AUDIO_CODEC select SND_SOC_SPDIF + select SND_SOC_SSM2305 select SND_SOC_SSM2518 if I2C select SND_SOC_SSM2602_SPI if SPI_MASTER select SND_SOC_SSM2602_I2C if I2C @@ -168,6 +172,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_TPA6130A2 if I2C select SND_SOC_TLV320DAC33 if I2C select SND_SOC_TSCS42XX if I2C + select SND_SOC_TSCS454 if I2C select SND_SOC_TS3A227E if I2C select SND_SOC_TWL4030 if TWL4030_CORE select SND_SOC_TWL6040 if TWL6040_CORE @@ -770,8 +775,10 @@ config SND_SOC_RL6231 default y if SND_SOC_RT5660=y default y if SND_SOC_RT5663=y default y if SND_SOC_RT5665=y + default y if SND_SOC_RT5668=y default y if SND_SOC_RT5670=y default y if SND_SOC_RT5677=y + default y if SND_SOC_RT1305=y default m if SND_SOC_RT5514=m default m if SND_SOC_RT5616=m default m if SND_SOC_RT5640=m @@ -781,8 +788,10 @@ config SND_SOC_RL6231 default m if SND_SOC_RT5660=m default m if SND_SOC_RT5663=m default m if SND_SOC_RT5665=m + default m if SND_SOC_RT5668=m default m if SND_SOC_RT5670=m default m if SND_SOC_RT5677=m + default m if SND_SOC_RT1305=m config SND_SOC_RL6347A tristate @@ -805,6 +814,9 @@ config SND_SOC_RT298 tristate depends on I2C +config SND_SOC_RT1305 + tristate + config SND_SOC_RT5514 tristate @@ -844,6 +856,9 @@ config SND_SOC_RT5663 config SND_SOC_RT5665 tristate +config SND_SOC_RT5668 + tristate + config SND_SOC_RT5670 tristate @@ -883,6 +898,12 @@ config SND_SOC_SIRF_AUDIO_CODEC config SND_SOC_SPDIF tristate "S/PDIF CODEC" +config SND_SOC_SSM2305 + tristate "Analog Devices SSM2305 Class-D Amplifier" + help + Enable support for Analog Devices SSM2305 filterless + high-efficiency mono Class-D audio power amplifiers. + config SND_SOC_SSM2518 tristate @@ -1011,6 +1032,13 @@ config SND_SOC_TSCS42XX help Add support for Tempo Semiconductor's TSCS42xx audio CODEC. +config SND_SOC_TSCS454 + tristate "Tempo Semiconductor TSCS454 CODEC" + depends on I2C + select REGMAP_I2C + help + Add support for Tempo Semiconductor's TSCS454 audio CODEC. + config SND_SOC_TWL4030 select MFD_TWL4030_AUDIO tristate @@ -1111,7 +1139,7 @@ config SND_SOC_WM8776 depends on SND_SOC_I2C_AND_SPI config SND_SOC_WM8782 - tristate + tristate "Wolfson Microelectronics WM8782 ADC" config SND_SOC_WM8804 tristate @@ -1247,6 +1275,9 @@ config SND_SOC_MC13783 config SND_SOC_ML26124 tristate +config SND_SOC_MT6351 + tristate "MediaTek MT6351 Codec" + config SND_SOC_NAU8540 tristate "Nuvoton Technology Corporation NAU85L40 CODEC" depends on I2C diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index e849d1495308..e023fdf85221 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -102,6 +102,7 @@ snd-soc-mc13783-objs := mc13783.o snd-soc-ml26124-objs := ml26124.o snd-soc-msm8916-analog-objs := msm8916-wcd-analog.o snd-soc-msm8916-digital-objs := msm8916-wcd-digital.o +snd-soc-mt6351-objs := mt6351.o snd-soc-nau8540-objs := nau8540.o snd-soc-nau8810-objs := nau8810.o snd-soc-nau8824-objs := nau8824.o @@ -126,6 +127,7 @@ snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o snd-soc-pcm512x-spi-objs := pcm512x-spi.o snd-soc-rl6231-objs := rl6231.o snd-soc-rl6347a-objs := rl6347a.o +snd-soc-rt1305-objs := rt1305.o snd-soc-rt274-objs := rt274.o snd-soc-rt286-objs := rt286.o snd-soc-rt298-objs := rt298.o @@ -140,6 +142,7 @@ snd-soc-rt5659-objs := rt5659.o snd-soc-rt5660-objs := rt5660.o snd-soc-rt5663-objs := rt5663.o snd-soc-rt5665-objs := rt5665.o +snd-soc-rt5668-objs := rt5668.o snd-soc-rt5670-objs := rt5670.o snd-soc-rt5677-objs := rt5677.o snd-soc-rt5677-spi-objs := rt5677-spi.o @@ -153,6 +156,7 @@ snd-soc-si476x-objs := si476x.o snd-soc-sirf-audio-codec-objs := sirf-audio-codec.o snd-soc-spdif-tx-objs := spdif_transmitter.o snd-soc-spdif-rx-objs := spdif_receiver.o +snd-soc-ssm2305-objs := ssm2305.o snd-soc-ssm2518-objs := ssm2518.o snd-soc-ssm2602-objs := ssm2602.o snd-soc-ssm2602-spi-objs := ssm2602-spi.o @@ -180,6 +184,7 @@ snd-soc-tlv320aic32x4-spi-objs := tlv320aic32x4-spi.o snd-soc-tlv320aic3x-objs := tlv320aic3x.o snd-soc-tlv320dac33-objs := tlv320dac33.o snd-soc-tscs42xx-objs := tscs42xx.o +snd-soc-tscs454-objs := tscs454.o snd-soc-ts3a227e-objs := ts3a227e.o snd-soc-twl4030-objs := twl4030.o snd-soc-twl6040-objs := twl6040.o @@ -355,6 +360,7 @@ obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o obj-$(CONFIG_SND_SOC_MSM8916_WCD_ANALOG) +=snd-soc-msm8916-analog.o obj-$(CONFIG_SND_SOC_MSM8916_WCD_DIGITAL) +=snd-soc-msm8916-digital.o +obj-$(CONFIG_SND_SOC_MT6351) += snd-soc-mt6351.o obj-$(CONFIG_SND_SOC_NAU8540) += snd-soc-nau8540.o obj-$(CONFIG_SND_SOC_NAU8810) += snd-soc-nau8810.o obj-$(CONFIG_SND_SOC_NAU8824) += snd-soc-nau8824.o @@ -379,6 +385,7 @@ obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o obj-$(CONFIG_SND_SOC_RL6347A) += snd-soc-rl6347a.o +obj-$(CONFIG_SND_SOC_RT1305) += snd-soc-rt1305.o obj-$(CONFIG_SND_SOC_RT274) += snd-soc-rt274.o obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o @@ -394,6 +401,7 @@ obj-$(CONFIG_SND_SOC_RT5659) += snd-soc-rt5659.o obj-$(CONFIG_SND_SOC_RT5660) += snd-soc-rt5660.o obj-$(CONFIG_SND_SOC_RT5663) += snd-soc-rt5663.o obj-$(CONFIG_SND_SOC_RT5665) += snd-soc-rt5665.o +obj-$(CONFIG_SND_SOC_RT5668) += snd-soc-rt5668.o obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o obj-$(CONFIG_SND_SOC_RT5677_SPI) += snd-soc-rt5677-spi.o @@ -404,6 +412,7 @@ obj-$(CONFIG_SND_SOC_SIGMADSP_REGMAP) += snd-soc-sigmadsp-regmap.o obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif-rx.o snd-soc-spdif-tx.o obj-$(CONFIG_SND_SOC_SIRF_AUDIO_CODEC) += sirf-audio-codec.o +obj-$(CONFIG_SND_SOC_SSM2305) += snd-soc-ssm2305.o obj-$(CONFIG_SND_SOC_SSM2518) += snd-soc-ssm2518.o obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o obj-$(CONFIG_SND_SOC_SSM2602_SPI) += snd-soc-ssm2602-spi.o @@ -432,6 +441,7 @@ obj-$(CONFIG_SND_SOC_TLV320AIC32X4_SPI) += snd-soc-tlv320aic32x4-spi.o obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o obj-$(CONFIG_SND_SOC_TLV320DAC33) += snd-soc-tlv320dac33.o obj-$(CONFIG_SND_SOC_TSCS42XX) += snd-soc-tscs42xx.o +obj-$(CONFIG_SND_SOC_TSCS454) += snd-soc-tscs454.o obj-$(CONFIG_SND_SOC_TS3A227E) += snd-soc-ts3a227e.o obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o diff --git a/sound/soc/codecs/adau17x1.c b/sound/soc/codecs/adau17x1.c index 12bf24c26818..ae41edd1c406 100644 --- a/sound/soc/codecs/adau17x1.c +++ b/sound/soc/codecs/adau17x1.c @@ -843,6 +843,15 @@ int adau17x1_setup_firmware(struct snd_soc_component *component, struct adau *adau = snd_soc_component_get_drvdata(component); struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + /* Check if sample rate is the same as before. If it is there is no + * point in performing the below steps as the call to + * sigmadsp_setup(...) will return directly when it finds the sample + * rate to be the same as before. By checking this we can prevent an + * audiable popping noise which occours when toggling DSP_RUN. + */ + if (adau->sigmadsp->current_samplerate == rate) + return 0; + snd_soc_dapm_mutex_lock(dapm); ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr); diff --git a/sound/soc/codecs/cs35l35.c b/sound/soc/codecs/cs35l35.c index a4a2cb171bdf..bd6226bde45f 100644 --- a/sound/soc/codecs/cs35l35.c +++ b/sound/soc/codecs/cs35l35.c @@ -1105,6 +1105,7 @@ static struct regmap_config cs35l35_regmap = { .readable_reg = cs35l35_readable_register, .precious_reg = cs35l35_precious_register, .cache_type = REGCACHE_RBTREE, + .use_single_rw = true, }; static irqreturn_t cs35l35_irq(int irq, void *data) diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c index 865f64c40b79..fb515aaa54fc 100644 --- a/sound/soc/codecs/max98088.c +++ b/sound/soc/codecs/max98088.c @@ -1382,15 +1382,12 @@ static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"}; static int max98088_get_channel(struct snd_soc_component *component, const char *name) { - int i; + int ret; - for (i = 0; i < ARRAY_SIZE(eq_mode_name); i++) - if (strcmp(name, eq_mode_name[i]) == 0) - return i; - - /* Shouldn't happen */ - dev_err(component->dev, "Bad EQ channel name '%s'\n", name); - return -EINVAL; + ret = match_string(eq_mode_name, ARRAY_SIZE(eq_mode_name), name); + if (ret < 0) + dev_err(component->dev, "Bad EQ channel name '%s'\n", name); + return ret; } static void max98088_setup_eq1(struct snd_soc_component *component) diff --git a/sound/soc/codecs/max98095.c b/sound/soc/codecs/max98095.c index 6bf2d0ba864f..3b3a10da7f40 100644 --- a/sound/soc/codecs/max98095.c +++ b/sound/soc/codecs/max98095.c @@ -1634,15 +1634,12 @@ static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"}; static int max98095_get_bq_channel(struct snd_soc_component *component, const char *name) { - int i; - - for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++) - if (strcmp(name, bq_mode_name[i]) == 0) - return i; + int ret; - /* Shouldn't happen */ - dev_err(component->dev, "Bad biquad channel name '%s'\n", name); - return -EINVAL; + ret = match_string(bq_mode_name, ARRAY_SIZE(bq_mode_name), name); + if (ret < 0) + dev_err(component->dev, "Bad biquad channel name '%s'\n", name); + return ret; } static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol, diff --git a/sound/soc/codecs/max9860.c b/sound/soc/codecs/max9860.c index 5bbf889ad98e..de3d44e9199b 100644 --- a/sound/soc/codecs/max9860.c +++ b/sound/soc/codecs/max9860.c @@ -1,23 +1,14 @@ -/* - * Driver for the MAX9860 Mono Audio Voice Codec - * - * https://datasheets.maximintegrated.com/en/ds/MAX9860.pdf - * - * The driver does not support sidetone since the DVST register field is - * backwards with the mute near the maximum level instead of the minimum. - * - * Author: Peter Rosin <peda@axentia.s> - * Copyright 2016 Axentia Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Driver for the MAX9860 Mono Audio Voice Codec +// +// https://datasheets.maximintegrated.com/en/ds/MAX9860.pdf +// +// The driver does not support sidetone since the DVST register field is +// backwards with the mute near the maximum level instead of the minimum. +// +// Author: Peter Rosin <peda@axentia.s> +// Copyright 2016 Axentia Technologies #include <linux/init.h> #include <linux/module.h> @@ -443,7 +434,8 @@ static int max9860_hw_params(struct snd_pcm_substream *substream, ret = regmap_update_bits(max9860->regmap, MAX9860_AUDIOCLKHIGH, MAX9860_PLL, MAX9860_PLL); if (ret) { - dev_err(component->dev, "Failed to enable PLL: %d\n", ret); + dev_err(component->dev, "Failed to enable PLL: %d\n", + ret); return ret; } } @@ -515,7 +507,8 @@ static int max9860_set_bias_level(struct snd_soc_component *component, ret = regmap_update_bits(max9860->regmap, MAX9860_PWRMAN, MAX9860_SHDN, MAX9860_SHDN); if (ret) { - dev_err(component->dev, "Failed to remove SHDN: %d\n", ret); + dev_err(component->dev, "Failed to remove SHDN: %d\n", + ret); return ret; } break; @@ -598,8 +591,7 @@ static const struct dev_pm_ops max9860_pm_ops = { SET_RUNTIME_PM_OPS(max9860_suspend, max9860_resume, NULL) }; -static int max9860_probe(struct i2c_client *i2c, - const struct i2c_device_id *id) +static int max9860_probe(struct i2c_client *i2c) { struct device *dev = &i2c->dev; struct max9860_priv *max9860; @@ -698,7 +690,7 @@ static int max9860_probe(struct i2c_client *i2c, pm_runtime_idle(dev); ret = devm_snd_soc_register_component(dev, &max9860_component_driver, - &max9860_dai, 1); + &max9860_dai, 1); if (ret) { dev_err(dev, "Failed to register CODEC: %d\n", ret); goto err_pm; @@ -736,7 +728,7 @@ static const struct of_device_id max9860_of_match[] = { MODULE_DEVICE_TABLE(of, max9860_of_match); static struct i2c_driver max9860_i2c_driver = { - .probe = max9860_probe, + .probe_new = max9860_probe, .remove = max9860_remove, .id_table = max9860_i2c_id, .driver = { diff --git a/sound/soc/codecs/max9860.h b/sound/soc/codecs/max9860.h index 22041bd67a7d..e07b905eaf50 100644 --- a/sound/soc/codecs/max9860.h +++ b/sound/soc/codecs/max9860.h @@ -1,17 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Driver for the MAX9860 Mono Audio Voice Codec * * Author: Peter Rosin <peda@axentia.s> * Copyright 2016 Axentia Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. */ #ifndef _SND_SOC_MAX9860 diff --git a/sound/soc/codecs/mt6351.c b/sound/soc/codecs/mt6351.c new file mode 100644 index 000000000000..f73dcd753584 --- /dev/null +++ b/sound/soc/codecs/mt6351.c @@ -0,0 +1,1505 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// mt6351.c -- mt6351 ALSA SoC audio codec driver +// +// Copyright (c) 2018 MediaTek Inc. +// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> + +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/delay.h> + +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/soc.h> +#include <sound/tlv.h> + +#include "mt6351.h" + +/* MT6351_TOP_CLKSQ */ +#define RG_CLKSQ_EN_AUD_BIT (0) + +/* MT6351_TOP_CKPDN_CON0 */ +#define RG_AUDNCP_CK_PDN_BIT (12) +#define RG_AUDIF_CK_PDN_BIT (13) +#define RG_AUD_CK_PDN_BIT (14) +#define RG_ZCD13M_CK_PDN_BIT (15) + +/* MT6351_AUDDEC_ANA_CON0 */ +#define RG_AUDDACLPWRUP_VAUDP32_BIT (0) +#define RG_AUDDACRPWRUP_VAUDP32_BIT (1) +#define RG_AUD_DAC_PWR_UP_VA32_BIT (2) +#define RG_AUD_DAC_PWL_UP_VA32_BIT (3) + +#define RG_AUDHSPWRUP_VAUDP32_BIT (4) + +#define RG_AUDHPLPWRUP_VAUDP32_BIT (5) +#define RG_AUDHPRPWRUP_VAUDP32_BIT (6) + +#define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT (7) +#define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK (0x3) + +#define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT (9) +#define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK (0x3) + +#define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT (11) +#define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK (0x3) + +#define RG_AUDHSSCDISABLE_VAUDP32 (13) +#define RG_AUDHPLSCDISABLE_VAUDP32_BIT (14) +#define RG_AUDHPRSCDISABLE_VAUDP32_BIT (15) + +/* MT6351_AUDDEC_ANA_CON1 */ +#define RG_HSOUTPUTSTBENH_VAUDP32_BIT (8) + +/* MT6351_AUDDEC_ANA_CON3 */ +#define RG_AUDLOLPWRUP_VAUDP32_BIT (2) + +#define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT (3) +#define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK (0x3) + +#define RG_AUDLOLSCDISABLE_VAUDP32_BIT (5) +#define RG_LOOUTPUTSTBENH_VAUDP32_BIT (9) + +/* MT6351_AUDDEC_ANA_CON6 */ +#define RG_ABIDEC_RSVD0_VAUDP32_HPL_BIT (8) +#define RG_ABIDEC_RSVD0_VAUDP32_HPR_BIT (9) +#define RG_ABIDEC_RSVD0_VAUDP32_HS_BIT (10) +#define RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT (11) + +/* MT6351_AUDDEC_ANA_CON9 */ +#define RG_AUDIBIASPWRDN_VAUDP32_BIT (8) +#define RG_RSTB_DECODER_VA32_BIT (9) +#define RG_AUDGLB_PWRDN_VA32_BIT (12) + +#define RG_LCLDO_DEC_EN_VA32_BIT (13) +#define RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT (15) +/* MT6351_AUDDEC_ANA_CON10 */ +#define RG_NVREG_EN_VAUDP32_BIT (8) + +#define RG_AUDGLB_LP2_VOW_EN_VA32 10 + +/* MT6351_AFE_UL_DL_CON0 */ +#define RG_AFE_ON_BIT (0) + +/* MT6351_AFE_DL_SRC2_CON0_L */ +#define RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT (0) + +/* MT6351_AFE_UL_SRC_CON0_L */ +#define UL_SRC_ON_TMP_CTL (0) + +/* MT6351_AFE_TOP_CON0 */ +#define RG_DL_SINE_ON_SFT (0) +#define RG_DL_SINE_ON_MASK (0x1) + +#define RG_UL_SINE_ON_SFT (1) +#define RG_UL_SINE_ON_MASK (0x1) + +/* MT6351_AUDIO_TOP_CON0 */ +#define AUD_TOP_PDN_RESERVED_BIT 0 +#define AUD_TOP_PWR_CLK_DIS_CTL_BIT 2 +#define AUD_TOP_PDN_ADC_CTL_BIT 5 +#define AUD_TOP_PDN_DAC_CTL_BIT 6 +#define AUD_TOP_PDN_AFE_CTL_BIT 7 + +/* MT6351_AFE_SGEN_CFG0 */ +#define SGEN_C_MUTE_SW_CTL_BIT 6 +#define SGEN_C_DAC_EN_CTL_BIT 7 + +/* MT6351_AFE_NCP_CFG0 */ +#define RG_NCP_ON_BIT 0 + +/* MT6351_LDO_VUSB33_CON0 */ +#define RG_VUSB33_EN 1 +#define RG_VUSB33_ON_CTRL 3 + +/* MT6351_LDO_VA18_CON0 */ +#define RG_VA18_EN 1 +#define RG_VA18_ON_CTRL 3 + +/* MT6351_AUDENC_ANA_CON0 */ +#define RG_AUDPREAMPLON 0 +#define RG_AUDPREAMPLDCCEN 1 +#define RG_AUDPREAMPLDCPRECHARGE 2 + +#define RG_AUDPREAMPLINPUTSEL_SFT (4) +#define RG_AUDPREAMPLINPUTSEL_MASK (0x3) + +#define RG_AUDADCLPWRUP 12 + +#define RG_AUDADCLINPUTSEL_SFT (13) +#define RG_AUDADCLINPUTSEL_MASK (0x3) + +/* MT6351_AUDENC_ANA_CON1 */ +#define RG_AUDPREAMPRON 0 +#define RG_AUDPREAMPRDCCEN 1 +#define RG_AUDPREAMPRDCPRECHARGE 2 + +#define RG_AUDPREAMPRINPUTSEL_SFT (4) +#define RG_AUDPREAMPRINPUTSEL_MASK (0x3) + +#define RG_AUDADCRPWRUP 12 + +#define RG_AUDADCRINPUTSEL_SFT (13) +#define RG_AUDADCRINPUTSEL_MASK (0x3) + +/* MT6351_AUDENC_ANA_CON3 */ +#define RG_AUDADCCLKRSTB 6 + +/* MT6351_AUDENC_ANA_CON9 */ +#define RG_AUDPWDBMICBIAS0 0 +#define RG_AUDMICBIAS0VREF 4 +#define RG_AUDMICBIAS0LOWPEN 7 + +#define RG_AUDPWDBMICBIAS2 8 +#define RG_AUDMICBIAS2VREF 12 +#define RG_AUDMICBIAS2LOWPEN 15 + +/* MT6351_AUDENC_ANA_CON10 */ +#define RG_AUDPWDBMICBIAS1 0 +#define RG_AUDMICBIAS1DCSW1NEN 2 +#define RG_AUDMICBIAS1VREF 4 +#define RG_AUDMICBIAS1LOWPEN 7 + +enum { + AUDIO_ANALOG_VOLUME_HSOUTL, + AUDIO_ANALOG_VOLUME_HSOUTR, + AUDIO_ANALOG_VOLUME_HPOUTL, + AUDIO_ANALOG_VOLUME_HPOUTR, + AUDIO_ANALOG_VOLUME_LINEOUTL, + AUDIO_ANALOG_VOLUME_LINEOUTR, + AUDIO_ANALOG_VOLUME_MICAMP1, + AUDIO_ANALOG_VOLUME_MICAMP2, + AUDIO_ANALOG_VOLUME_TYPE_MAX +}; + +/* Supply subseq */ +enum { + SUPPLY_SUBSEQ_SETTING, + SUPPLY_SUBSEQ_ENABLE, + SUPPLY_SUBSEQ_MICBIAS, +}; + +#define REG_STRIDE 2 + +struct mt6351_priv { + struct device *dev; + struct regmap *regmap; + + unsigned int dl_rate; + unsigned int ul_rate; + + int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX]; + + int hp_en_counter; +}; + +static void set_hp_gain_zero(struct snd_soc_component *cmpnt) +{ + regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2, + 0x1f << 7, 0x8 << 7); + regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2, + 0x1f << 0, 0x8 << 0); +} + +static unsigned int get_cap_reg_val(struct snd_soc_component *cmpnt, + unsigned int rate) +{ + switch (rate) { + case 8000: + return 0; + case 16000: + return 1; + case 32000: + return 2; + case 48000: + return 3; + case 96000: + return 4; + case 192000: + return 5; + default: + dev_warn(cmpnt->dev, "%s(), error rate %d, return 3", + __func__, rate); + return 3; + } +} + +static unsigned int get_play_reg_val(struct snd_soc_component *cmpnt, + unsigned int rate) +{ + switch (rate) { + case 8000: + return 0; + case 11025: + return 1; + case 12000: + return 2; + case 16000: + return 3; + case 22050: + return 4; + case 24000: + return 5; + case 32000: + return 6; + case 44100: + return 7; + case 48000: + case 96000: + case 192000: + return 8; + default: + dev_warn(cmpnt->dev, "%s(), error rate %d, return 8", + __func__, rate); + return 8; + } +} + +static int mt6351_codec_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *cmpnt = dai->component; + struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); + unsigned int rate = params_rate(params); + + dev_dbg(priv->dev, "%s(), substream->stream %d, rate %d\n", + __func__, substream->stream, rate); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + priv->dl_rate = rate; + else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) + priv->ul_rate = rate; + + return 0; +} + +static const struct snd_soc_dai_ops mt6351_codec_dai_ops = { + .hw_params = mt6351_codec_dai_hw_params, +}; + +#define MT6351_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\ + SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\ + SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\ + SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\ + SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE) + +static struct snd_soc_dai_driver mt6351_dai_driver[] = { + { + .name = "mt6351-snd-codec-aif1", + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000 | + SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = MT6351_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | + SNDRV_PCM_RATE_32000 | + SNDRV_PCM_RATE_48000 | + SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = MT6351_FORMATS, + }, + .ops = &mt6351_codec_dai_ops, + }, +}; + +enum { + HP_GAIN_SET_ZERO, + HP_GAIN_RESTORE, +}; + +static void hp_gain_ramp_set(struct snd_soc_component *cmpnt, int hp_gain_ctl) +{ + struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); + int idx, old_idx, offset, reg_idx; + + if (hp_gain_ctl == HP_GAIN_SET_ZERO) { + idx = 8; /* 0dB */ + old_idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]; + } else { + idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]; + old_idx = 8; /* 0dB */ + } + dev_dbg(priv->dev, "%s(), idx %d, old_idx %d\n", + __func__, idx, old_idx); + + if (idx > old_idx) + offset = idx - old_idx; + else + offset = old_idx - idx; + + reg_idx = old_idx; + + while (offset > 0) { + reg_idx = idx > old_idx ? reg_idx + 1 : reg_idx - 1; + + /* check valid range, and set value */ + if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) { + regmap_update_bits(cmpnt->regmap, + MT6351_ZCD_CON2, + 0xf9f, + (reg_idx << 7) | reg_idx); + usleep_range(100, 120); + } + offset--; + } +} + +static void hp_zcd_enable(struct snd_soc_component *cmpnt) +{ + /* Enable ZCD, for minimize pop noise */ + /* when adjust gain during HP buffer on */ + regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 8, 0x1 << 8); + regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 7, 0x0 << 7); + + /* timeout, 1=5ms, 0=30ms */ + regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 6, 0x1 << 6); + + regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x3 << 4, 0x0 << 4); + regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 1, 0x5 << 1); + regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 0, 0x1 << 0); +} + +static void hp_zcd_disable(struct snd_soc_component *cmpnt) +{ + regmap_write(cmpnt->regmap, MT6351_ZCD_CON0, 0x0000); +} + +static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0); +static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0); + +static const struct snd_kcontrol_new mt6351_snd_controls[] = { + /* dl pga gain */ + SOC_DOUBLE_TLV("Headphone Volume", + MT6351_ZCD_CON2, 0, 7, 0x12, 1, + playback_tlv), + SOC_DOUBLE_TLV("Lineout Volume", + MT6351_ZCD_CON1, 0, 7, 0x12, 1, + playback_tlv), + SOC_SINGLE_TLV("Handset Volume", + MT6351_ZCD_CON3, 0, 0x12, 1, + playback_tlv), + /* ul pga gain */ + SOC_DOUBLE_R_TLV("PGA Volume", + MT6351_AUDENC_ANA_CON0, MT6351_AUDENC_ANA_CON1, + 8, 4, 0, + pga_tlv), +}; + +/* MUX */ + +/* LOL MUX */ +static const char *const lo_in_mux_map[] = { + "Open", "Mute", "Playback", "Test Mode", +}; + +static int lo_in_mux_map_value[] = { + 0x0, 0x1, 0x2, 0x3, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum, + MT6351_AUDDEC_ANA_CON3, + RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT, + RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK, + lo_in_mux_map, + lo_in_mux_map_value); + +static const struct snd_kcontrol_new lo_in_mux_control = + SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum); + +/*HP MUX */ +static const char *const hp_in_mux_map[] = { + "Open", "LoudSPK Playback", "Audio Playback", "Test Mode", +}; + +static int hp_in_mux_map_value[] = { + 0x0, 0x1, 0x2, 0x3, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum, + MT6351_AUDDEC_ANA_CON0, + RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT, + RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK, + hp_in_mux_map, + hp_in_mux_map_value); + +static const struct snd_kcontrol_new hpl_in_mux_control = + SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum, + MT6351_AUDDEC_ANA_CON0, + RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT, + RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK, + hp_in_mux_map, + hp_in_mux_map_value); + +static const struct snd_kcontrol_new hpr_in_mux_control = + SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum); + +/* RCV MUX */ +static const char *const rcv_in_mux_map[] = { + "Open", "Mute", "Voice Playback", "Test Mode", +}; + +static int rcv_in_mux_map_value[] = { + 0x0, 0x1, 0x2, 0x3, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum, + MT6351_AUDDEC_ANA_CON0, + RG_AUDHSMUXINPUTSEL_VAUDP32_SFT, + RG_AUDHSMUXINPUTSEL_VAUDP32_MASK, + rcv_in_mux_map, + rcv_in_mux_map_value); + +static const struct snd_kcontrol_new rcv_in_mux_control = + SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum); + +/* DAC In MUX */ +static const char *const dac_in_mux_map[] = { + "Normal Path", "Sgen", +}; + +static int dac_in_mux_map_value[] = { + 0x0, 0x1, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum, + MT6351_AFE_TOP_CON0, + RG_DL_SINE_ON_SFT, + RG_DL_SINE_ON_MASK, + dac_in_mux_map, + dac_in_mux_map_value); + +static const struct snd_kcontrol_new dac_in_mux_control = + SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum); + +/* AIF Out MUX */ +static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum, + MT6351_AFE_TOP_CON0, + RG_UL_SINE_ON_SFT, + RG_UL_SINE_ON_MASK, + dac_in_mux_map, + dac_in_mux_map_value); + +static const struct snd_kcontrol_new aif_out_mux_control = + SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum); + +/* ADC L MUX */ +static const char *const adc_left_mux_map[] = { + "Idle", "AIN0", "Left Preamplifier", "Idle_1", +}; + +static int adc_left_mux_map_value[] = { + 0x0, 0x1, 0x2, 0x3, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum, + MT6351_AUDENC_ANA_CON0, + RG_AUDADCLINPUTSEL_SFT, + RG_AUDADCLINPUTSEL_MASK, + adc_left_mux_map, + adc_left_mux_map_value); + +static const struct snd_kcontrol_new adc_left_mux_control = + SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum); + +/* ADC R MUX */ +static const char *const adc_right_mux_map[] = { + "Idle", "AIN0", "Right Preamplifier", "Idle_1", +}; + +static int adc_right_mux_map_value[] = { + 0x0, 0x1, 0x2, 0x3, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum, + MT6351_AUDENC_ANA_CON1, + RG_AUDADCRINPUTSEL_SFT, + RG_AUDADCRINPUTSEL_MASK, + adc_right_mux_map, + adc_right_mux_map_value); + +static const struct snd_kcontrol_new adc_right_mux_control = + SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum); + +/* PGA L MUX */ +static const char *const pga_left_mux_map[] = { + "None", "AIN0", "AIN1", "AIN2", +}; + +static int pga_left_mux_map_value[] = { + 0x0, 0x1, 0x2, 0x3, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum, + MT6351_AUDENC_ANA_CON0, + RG_AUDPREAMPLINPUTSEL_SFT, + RG_AUDPREAMPLINPUTSEL_MASK, + pga_left_mux_map, + pga_left_mux_map_value); + +static const struct snd_kcontrol_new pga_left_mux_control = + SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum); + +/* PGA R MUX */ +static const char *const pga_right_mux_map[] = { + "None", "AIN0", "AIN3", "AIN2", +}; + +static int pga_right_mux_map_value[] = { + 0x0, 0x1, 0x2, 0x3, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum, + MT6351_AUDENC_ANA_CON1, + RG_AUDPREAMPRINPUTSEL_SFT, + RG_AUDPREAMPRINPUTSEL_MASK, + pga_right_mux_map, + pga_right_mux_map_value); + +static const struct snd_kcontrol_new pga_right_mux_control = + SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum); + +static int mt_reg_set_clr_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (w->on_val) { + /* SET REG */ + regmap_update_bits(cmpnt->regmap, + w->reg + REG_STRIDE, + 0x1 << w->shift, + 0x1 << w->shift); + } else { + /* CLR REG */ + regmap_update_bits(cmpnt->regmap, + w->reg + REG_STRIDE * 2, + 0x1 << w->shift, + 0x1 << w->shift); + } + break; + case SND_SOC_DAPM_PRE_PMD: + if (w->off_val) { + /* SET REG */ + regmap_update_bits(cmpnt->regmap, + w->reg + REG_STRIDE, + 0x1 << w->shift, + 0x1 << w->shift); + } else { + /* CLR REG */ + regmap_update_bits(cmpnt->regmap, + w->reg + REG_STRIDE * 2, + 0x1 << w->shift, + 0x1 << w->shift); + } + break; + default: + break; + } + + return 0; +} + +static int mt_ncp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG1, + 0xffff, 0x1515); + /* NCP: ck1 and ck2 clock frequecy adjust configure */ + regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG0, + 0xfffe, 0x8C00); + break; + case SND_SOC_DAPM_POST_PMU: + usleep_range(250, 270); + break; + default: + break; + } + + return 0; +} + +static int mt_sgen_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG0, + 0xffef, 0x0008); + regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG1, + 0xffff, 0x0101); + break; + default: + break; + } + + return 0; +} + +static int mt_aif_in_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); + + dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", + __func__, event, priv->dl_rate); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* sdm audio fifo clock power on */ + regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2, + 0xffff, 0x0006); + /* scrambler clock on enable */ + regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON0, + 0xffff, 0xC3A1); + /* sdm power on */ + regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2, + 0xffff, 0x0003); + /* sdm fifo enable */ + regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2, + 0xffff, 0x000B); + /* set attenuation gain */ + regmap_update_bits(cmpnt->regmap, MT6351_AFE_DL_SDM_CON1, + 0xffff, 0x001E); + + regmap_write(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG0, + (get_play_reg_val(cmpnt, priv->dl_rate) << 12) | + 0x330); + regmap_write(cmpnt->regmap, MT6351_AFE_DL_SRC2_CON0_H, + (get_play_reg_val(cmpnt, priv->dl_rate) << 12) | + 0x300); + + regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2, + 0x8000, 0x8000); + break; + default: + break; + } + + return 0; +} + +static int mt_hp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); + int reg; + + dev_dbg(priv->dev, "%s(), event 0x%x, hp_en_counter %d\n", + __func__, event, priv->hp_en_counter); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + priv->hp_en_counter++; + if (priv->hp_en_counter > 1) + break; /* already enabled, do nothing */ + else if (priv->hp_en_counter <= 0) + dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n", + __func__, + priv->hp_en_counter); + + hp_zcd_disable(cmpnt); + + /* from yoyo HQA script */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6, + 0x0700, 0x0700); + + /* save target gain to restore after hardware open complete */ + regmap_read(cmpnt->regmap, MT6351_ZCD_CON2, ®); + priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = reg & 0x1f; + priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = (reg >> 7) & 0x1f; + + /* Set HPR/HPL gain as minimum (~ -40dB) */ + regmap_update_bits(cmpnt->regmap, + MT6351_ZCD_CON2, 0xffff, 0x0F9F); + /* Set HS gain as minimum (~ -40dB) */ + regmap_update_bits(cmpnt->regmap, + MT6351_ZCD_CON3, 0xffff, 0x001F); + /* De_OSC of HP */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON2, + 0x0001, 0x0001); + /* enable output STBENH */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1, + 0xffff, 0x2000); + /* De_OSC of voice, enable output STBENH */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1, + 0xffff, 0x2100); + /* Enable voice driver */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0, + 0x0010, 0xE090); + /* Enable pre-charge buffer */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1, + 0xffff, 0x2140); + + usleep_range(50, 60); + + /* Apply digital DC compensation value to DAC */ + set_hp_gain_zero(cmpnt); + + /* Enable HPR/HPL */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1, + 0xffff, 0x2100); + /* Disable pre-charge buffer */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1, + 0xffff, 0x2000); + /* Disable De_OSC of voice */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0, + 0x0010, 0xF4EF); + /* Disable voice buffer */ + + /* from yoyo HQ */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6, + 0x0700, 0x0300); + + /* Enable ZCD, for minimize pop noise */ + /* when adjust gain during HP buffer on */ + hp_zcd_enable(cmpnt); + + /* apply volume setting */ + hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE); + + break; + case SND_SOC_DAPM_PRE_PMD: + priv->hp_en_counter--; + if (priv->hp_en_counter > 0) + break; /* still being used, don't close */ + else if (priv->hp_en_counter < 0) + dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n", + __func__, + priv->hp_en_counter); + + /* Disable AUD_ZCD */ + hp_zcd_disable(cmpnt); + + /* Set HPR/HPL gain as -1dB, step by step */ + hp_gain_ramp_set(cmpnt, HP_GAIN_SET_ZERO); + + set_hp_gain_zero(cmpnt); + break; + case SND_SOC_DAPM_POST_PMD: + if (priv->hp_en_counter > 0) + break; /* still being used, don't close */ + else if (priv->hp_en_counter < 0) + dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n", + __func__, + priv->hp_en_counter); + + /* reset*/ + regmap_update_bits(cmpnt->regmap, + MT6351_AUDDEC_ANA_CON6, + 0x0700, + 0x0000); + /* De_OSC of HP */ + regmap_update_bits(cmpnt->regmap, + MT6351_AUDDEC_ANA_CON2, + 0x0001, + 0x0000); + + /* apply volume setting */ + hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE); + break; + default: + break; + } + + return 0; +} + +static int mt_aif_out_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); + + dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", + __func__, event, priv->ul_rate); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* dcclk_div=11'b00100000011, dcclk_ref_ck_sel=2'b00 */ + regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0, + 0xffff, 0x2062); + /* dcclk_pdn=1'b0 */ + regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0, + 0xffff, 0x2060); + /* dcclk_gen_on=1'b1 */ + regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0, + 0xffff, 0x2061); + + /* UL sample rate and mode configure */ + regmap_update_bits(cmpnt->regmap, MT6351_AFE_UL_SRC_CON0_H, + 0x000E, + get_cap_reg_val(cmpnt, priv->ul_rate) << 1); + + /* fixed 260k path for 8/16/32/48 */ + if (priv->ul_rate <= 48000) { + /* anc ul path src on */ + regmap_update_bits(cmpnt->regmap, + MT6351_AFE_HPANC_CFG0, + 0x1 << 1, + 0x1 << 1); + /* ANC clk pdn release */ + regmap_update_bits(cmpnt->regmap, + MT6351_AFE_HPANC_CFG0, + 0x1 << 0, + 0x0 << 0); + } + break; + case SND_SOC_DAPM_PRE_PMD: + /* fixed 260k path for 8/16/32/48 */ + if (priv->ul_rate <= 48000) { + /* anc ul path src on */ + regmap_update_bits(cmpnt->regmap, + MT6351_AFE_HPANC_CFG0, + 0x1 << 1, + 0x0 << 1); + /* ANC clk pdn release */ + regmap_update_bits(cmpnt->regmap, + MT6351_AFE_HPANC_CFG0, + 0x1 << 0, + 0x1 << 0); + } + break; + default: + break; + } + + return 0; +} + +static int mt_adc_clkgen_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* Audio ADC clock gen. mode: 00_divided by 2 (Normal) */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3, + 0x3 << 4, 0x0); + break; + case SND_SOC_DAPM_POST_PMU: + /* ADC CLK from: 00_13MHz from CLKSQ (Default) */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3, + 0x3 << 2, 0x0); + break; + default: + break; + } + return 0; +} + +static int mt_pga_left_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* Audio L PGA precharge on */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0, + 0x3 << RG_AUDPREAMPLDCPRECHARGE, + 0x1 << RG_AUDPREAMPLDCPRECHARGE); + /* Audio L PGA mode: 1_DCC */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0, + 0x3 << RG_AUDPREAMPLDCCEN, + 0x1 << RG_AUDPREAMPLDCCEN); + break; + case SND_SOC_DAPM_POST_PMU: + usleep_range(100, 120); + /* Audio L PGA precharge off */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0, + 0x3 << RG_AUDPREAMPLDCPRECHARGE, + 0x0 << RG_AUDPREAMPLDCPRECHARGE); + break; + default: + break; + } + return 0; +} + +static int mt_pga_right_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* Audio R PGA precharge on */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1, + 0x3 << RG_AUDPREAMPRDCPRECHARGE, + 0x1 << RG_AUDPREAMPRDCPRECHARGE); + /* Audio R PGA mode: 1_DCC */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1, + 0x3 << RG_AUDPREAMPRDCCEN, + 0x1 << RG_AUDPREAMPRDCCEN); + break; + case SND_SOC_DAPM_POST_PMU: + usleep_range(100, 120); + /* Audio R PGA precharge off */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1, + 0x3 << RG_AUDPREAMPRDCPRECHARGE, + 0x0 << RG_AUDPREAMPRDCPRECHARGE); + break; + default: + break; + } + return 0; +} + +static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* MIC Bias 0 LowPower: 0_Normal */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, + 0x3 << RG_AUDMICBIAS0LOWPEN, 0x0); + /* MISBIAS0 = 1P9V */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, + 0x7 << RG_AUDMICBIAS0VREF, + 0x2 << RG_AUDMICBIAS0VREF); + break; + case SND_SOC_DAPM_POST_PMD: + /* MISBIAS0 = 1P97 */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, + 0x7 << RG_AUDMICBIAS0VREF, + 0x0 << RG_AUDMICBIAS0VREF); + break; + default: + break; + } + return 0; +} + +static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* MIC Bias 1 LowPower: 0_Normal */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10, + 0x3 << RG_AUDMICBIAS1LOWPEN, 0x0); + /* MISBIAS1 = 2P7V */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10, + 0x7 << RG_AUDMICBIAS1VREF, + 0x7 << RG_AUDMICBIAS1VREF); + break; + case SND_SOC_DAPM_POST_PMD: + /* MISBIAS1 = 1P7V */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10, + 0x7 << RG_AUDMICBIAS1VREF, + 0x0 << RG_AUDMICBIAS1VREF); + break; + default: + break; + } + return 0; +} + +static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* MIC Bias 2 LowPower: 0_Normal */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, + 0x3 << RG_AUDMICBIAS2LOWPEN, 0x0); + /* MISBIAS2 = 1P9V */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, + 0x7 << RG_AUDMICBIAS2VREF, + 0x2 << RG_AUDMICBIAS2VREF); + break; + case SND_SOC_DAPM_POST_PMD: + /* MISBIAS2 = 1P97 */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, + 0x7 << RG_AUDMICBIAS2VREF, + 0x0 << RG_AUDMICBIAS2VREF); + break; + default: + break; + } + return 0; +} + +/* DAPM Kcontrols */ +static const struct snd_kcontrol_new mt_lineout_control = + SOC_DAPM_SINGLE("Switch", MT6351_AUDDEC_ANA_CON3, + RG_AUDLOLPWRUP_VAUDP32_BIT, 1, 0); + +/* DAPM Widgets */ +static const struct snd_soc_dapm_widget mt6351_dapm_widgets[] = { + /* Digital Clock */ + SND_SOC_DAPM_SUPPLY("AUDIO_TOP_AFE_CTL", MT6351_AUDIO_TOP_CON0, + AUD_TOP_PDN_AFE_CTL_BIT, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("AUDIO_TOP_DAC_CTL", MT6351_AUDIO_TOP_CON0, + AUD_TOP_PDN_DAC_CTL_BIT, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("AUDIO_TOP_ADC_CTL", MT6351_AUDIO_TOP_CON0, + AUD_TOP_PDN_ADC_CTL_BIT, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PWR_CLK", MT6351_AUDIO_TOP_CON0, + AUD_TOP_PWR_CLK_DIS_CTL_BIT, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PDN_RESERVED", MT6351_AUDIO_TOP_CON0, + AUD_TOP_PDN_RESERVED_BIT, 1, NULL, 0), + + SND_SOC_DAPM_SUPPLY("NCP", MT6351_AFE_NCP_CFG0, + RG_NCP_ON_BIT, 0, + mt_ncp_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + + SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM, + 0, 0, NULL, 0), + + /* Global Supply*/ + SND_SOC_DAPM_SUPPLY("AUDGLB", MT6351_AUDDEC_ANA_CON9, + RG_AUDGLB_PWRDN_VA32_BIT, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLKSQ Audio", MT6351_TOP_CLKSQ, + RG_CLKSQ_EN_AUD_BIT, 0, + mt_reg_set_clr_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_SUPPLY("ZCD13M_CK", MT6351_TOP_CKPDN_CON0, + RG_ZCD13M_CK_PDN_BIT, 1, + mt_reg_set_clr_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_SUPPLY("AUD_CK", MT6351_TOP_CKPDN_CON0, + RG_AUD_CK_PDN_BIT, 1, + mt_reg_set_clr_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_SUPPLY("AUDIF_CK", MT6351_TOP_CKPDN_CON0, + RG_AUDIF_CK_PDN_BIT, 1, + mt_reg_set_clr_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_SUPPLY("AUDNCP_CK", MT6351_TOP_CKPDN_CON0, + RG_AUDNCP_CK_PDN_BIT, 1, + mt_reg_set_clr_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_SUPPLY("AFE_ON", MT6351_AFE_UL_DL_CON0, RG_AFE_ON_BIT, 0, + NULL, 0), + + /* AIF Rx*/ + SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0, + MT6351_AFE_DL_SRC2_CON0_L, + RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0, + mt_aif_in_event, SND_SOC_DAPM_PRE_PMU), + + /* DL Supply */ + SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM, + 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("NV Regulator", MT6351_AUDDEC_ANA_CON10, + RG_NVREG_EN_VAUDP32_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("AUD_CLK", MT6351_AUDDEC_ANA_CON9, + RG_RSTB_DECODER_VA32_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("IBIST", MT6351_AUDDEC_ANA_CON9, + RG_AUDIBIASPWRDN_VAUDP32_BIT, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("LDO", MT6351_AUDDEC_ANA_CON9, + RG_LCLDO_DEC_EN_VA32_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("LDO_REMOTE_SENSE", MT6351_AUDDEC_ANA_CON9, + RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT, 0, NULL, 0), + + /* DAC */ + SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control), + + SND_SOC_DAPM_DAC("DACL", NULL, MT6351_AUDDEC_ANA_CON0, + RG_AUDDACLPWRUP_VAUDP32_BIT, 0), + SND_SOC_DAPM_SUPPLY("DACL_BIASGEN", MT6351_AUDDEC_ANA_CON0, + RG_AUD_DAC_PWL_UP_VA32_BIT, 0, NULL, 0), + + SND_SOC_DAPM_DAC("DACR", NULL, MT6351_AUDDEC_ANA_CON0, + RG_AUDDACRPWRUP_VAUDP32_BIT, 0), + SND_SOC_DAPM_SUPPLY("DACR_BIASGEN", MT6351_AUDDEC_ANA_CON0, + RG_AUD_DAC_PWR_UP_VA32_BIT, 0, NULL, 0), + /* LOL */ + SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control), + + SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6351_AUDDEC_ANA_CON3, + RG_LOOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("LOL Bias Gen", MT6351_AUDDEC_ANA_CON6, + RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT, 0, NULL, 0), + + SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6351_AUDDEC_ANA_CON3, + RG_AUDLOLPWRUP_VAUDP32_BIT, 0, NULL, 0), + + /* Headphone */ + SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_in_mux_control), + SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_in_mux_control), + + SND_SOC_DAPM_OUT_DRV_E("HPL Power", MT6351_AUDDEC_ANA_CON0, + RG_AUDHPLPWRUP_VAUDP32_BIT, 0, NULL, 0, + mt_hp_event, + SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_PRE_PMD | + SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_OUT_DRV_E("HPR Power", MT6351_AUDDEC_ANA_CON0, + RG_AUDHPRPWRUP_VAUDP32_BIT, 0, NULL, 0, + mt_hp_event, + SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_PRE_PMD | + SND_SOC_DAPM_POST_PMD), + + /* Receiver */ + SND_SOC_DAPM_MUX("RCV Mux", SND_SOC_NOPM, 0, 0, &rcv_in_mux_control), + + SND_SOC_DAPM_SUPPLY("RCV Stability Enh", MT6351_AUDDEC_ANA_CON1, + RG_HSOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RCV Bias Gen", MT6351_AUDDEC_ANA_CON6, + RG_ABIDEC_RSVD0_VAUDP32_HS_BIT, 0, NULL, 0), + + SND_SOC_DAPM_OUT_DRV("RCV Buffer", MT6351_AUDDEC_ANA_CON0, + RG_AUDHSPWRUP_VAUDP32_BIT, 0, NULL, 0), + + /* Outputs */ + SND_SOC_DAPM_OUTPUT("Receiver"), + SND_SOC_DAPM_OUTPUT("Headphone L"), + SND_SOC_DAPM_OUTPUT("Headphone R"), + SND_SOC_DAPM_OUTPUT("LINEOUT L"), + + /* SGEN */ + SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6351_AFE_SGEN_CFG0, + SGEN_C_DAC_EN_CTL_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6351_AFE_SGEN_CFG0, + SGEN_C_MUTE_SW_CTL_BIT, 1, + mt_sgen_event, SND_SOC_DAPM_PRE_PMU), + SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6351_AFE_DL_SRC2_CON0_L, + RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0, NULL, 0), + + SND_SOC_DAPM_INPUT("SGEN DL"), + + /* Uplinks */ + SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0, + MT6351_AFE_UL_SRC_CON0_L, + UL_SRC_ON_TMP_CTL, 0, + mt_aif_out_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO", SUPPLY_SUBSEQ_ENABLE, + MT6351_LDO_VUSB33_CON0, RG_VUSB33_EN, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO_CTRL", SUPPLY_SUBSEQ_SETTING, + MT6351_LDO_VUSB33_CON0, RG_VUSB33_ON_CTRL, 1, + NULL, 0), + + SND_SOC_DAPM_SUPPLY_S("VA18_LDO", SUPPLY_SUBSEQ_ENABLE, + MT6351_LDO_VA18_CON0, RG_VA18_EN, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY_S("VA18_LDO_CTRL", SUPPLY_SUBSEQ_SETTING, + MT6351_LDO_VA18_CON0, RG_VA18_ON_CTRL, 1, + NULL, 0), + + SND_SOC_DAPM_SUPPLY_S("ADC CLKGEN", SUPPLY_SUBSEQ_ENABLE, + MT6351_AUDENC_ANA_CON3, RG_AUDADCCLKRSTB, 0, + mt_adc_clkgen_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + + /* Uplinks MUX */ + SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0, + &aif_out_mux_control), + + SND_SOC_DAPM_MUX("ADC L Mux", SND_SOC_NOPM, 0, 0, + &adc_left_mux_control), + SND_SOC_DAPM_MUX("ADC R Mux", SND_SOC_NOPM, 0, 0, + &adc_right_mux_control), + + SND_SOC_DAPM_ADC("ADC L", NULL, + MT6351_AUDENC_ANA_CON0, RG_AUDADCLPWRUP, 0), + SND_SOC_DAPM_ADC("ADC R", NULL, + MT6351_AUDENC_ANA_CON1, RG_AUDADCRPWRUP, 0), + + SND_SOC_DAPM_MUX("PGA L Mux", SND_SOC_NOPM, 0, 0, + &pga_left_mux_control), + SND_SOC_DAPM_MUX("PGA R Mux", SND_SOC_NOPM, 0, 0, + &pga_right_mux_control), + + SND_SOC_DAPM_PGA_E("PGA L", MT6351_AUDENC_ANA_CON0, RG_AUDPREAMPLON, 0, + NULL, 0, + mt_pga_left_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_PGA_E("PGA R", MT6351_AUDENC_ANA_CON1, RG_AUDPREAMPRON, 0, + NULL, 0, + mt_pga_right_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + + /* main mic mic bias */ + SND_SOC_DAPM_SUPPLY_S("Mic Bias 0", SUPPLY_SUBSEQ_MICBIAS, + MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS0, 0, + mt_mic_bias_0_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + /* ref mic mic bias */ + SND_SOC_DAPM_SUPPLY_S("Mic Bias 2", SUPPLY_SUBSEQ_MICBIAS, + MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS2, 0, + mt_mic_bias_2_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + /* headset mic1/2 mic bias */ + SND_SOC_DAPM_SUPPLY_S("Mic Bias 1", SUPPLY_SUBSEQ_MICBIAS, + MT6351_AUDENC_ANA_CON10, RG_AUDPWDBMICBIAS1, 0, + mt_mic_bias_1_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S("Mic Bias 1 DCC pull high", SUPPLY_SUBSEQ_MICBIAS, + MT6351_AUDENC_ANA_CON10, + RG_AUDMICBIAS1DCSW1NEN, 0, + NULL, 0), + + /* UL input */ + SND_SOC_DAPM_INPUT("AIN0"), + SND_SOC_DAPM_INPUT("AIN1"), + SND_SOC_DAPM_INPUT("AIN2"), + SND_SOC_DAPM_INPUT("AIN3"), +}; + +static const struct snd_soc_dapm_route mt6351_dapm_routes[] = { + /* Capture */ + {"AIF1TX", NULL, "AIF Out Mux"}, + {"AIF1TX", NULL, "VUSB33_LDO"}, + {"VUSB33_LDO", NULL, "VUSB33_LDO_CTRL"}, + {"AIF1TX", NULL, "VA18_LDO"}, + {"VA18_LDO", NULL, "VA18_LDO_CTRL"}, + + {"AIF1TX", NULL, "AUDGLB"}, + {"AIF1TX", NULL, "CLKSQ Audio"}, + + {"AIF1TX", NULL, "AFE_ON"}, + + {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"}, + {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"}, + {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"}, + {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"}, + + {"AIF Out Mux", "Normal Path", "ADC L"}, + {"AIF Out Mux", "Normal Path", "ADC R"}, + + {"ADC L", NULL, "ADC L Mux"}, + {"ADC L", NULL, "AUD_CK"}, + {"ADC L", NULL, "AUDIF_CK"}, + {"ADC L", NULL, "ADC CLKGEN"}, + {"ADC R", NULL, "ADC R Mux"}, + {"ADC R", NULL, "AUD_CK"}, + {"ADC R", NULL, "AUDIF_CK"}, + {"ADC R", NULL, "ADC CLKGEN"}, + + {"ADC L Mux", "AIN0", "AIN0"}, + {"ADC L Mux", "Left Preamplifier", "PGA L"}, + + {"ADC R Mux", "AIN0", "AIN0"}, + {"ADC R Mux", "Right Preamplifier", "PGA R"}, + + {"PGA L", NULL, "PGA L Mux"}, + {"PGA R", NULL, "PGA R Mux"}, + + {"PGA L Mux", "AIN0", "AIN0"}, + {"PGA L Mux", "AIN1", "AIN1"}, + {"PGA L Mux", "AIN2", "AIN2"}, + + {"PGA R Mux", "AIN0", "AIN0"}, + {"PGA R Mux", "AIN3", "AIN3"}, + {"PGA R Mux", "AIN2", "AIN2"}, + + {"AIN0", NULL, "Mic Bias 0"}, + {"AIN2", NULL, "Mic Bias 2"}, + + {"AIN1", NULL, "Mic Bias 1"}, + {"AIN1", NULL, "Mic Bias 1 DCC pull high"}, + + /* DL Supply */ + {"DL Power Supply", NULL, "AUDGLB"}, + {"DL Power Supply", NULL, "CLKSQ Audio"}, + {"DL Power Supply", NULL, "ZCD13M_CK"}, + {"DL Power Supply", NULL, "AUD_CK"}, + {"DL Power Supply", NULL, "AUDIF_CK"}, + {"DL Power Supply", NULL, "AUDNCP_CK"}, + + {"DL Power Supply", NULL, "NV Regulator"}, + {"DL Power Supply", NULL, "AUD_CLK"}, + {"DL Power Supply", NULL, "IBIST"}, + {"DL Power Supply", NULL, "LDO"}, + {"LDO", NULL, "LDO_REMOTE_SENSE"}, + + /* DL Digital Supply */ + {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"}, + {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"}, + {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"}, + {"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"}, + {"DL Digital Clock", NULL, "NCP"}, + {"DL Digital Clock", NULL, "AFE_ON"}, + + {"AIF_RX", NULL, "DL Digital Clock"}, + + /* DL Path */ + {"DAC In Mux", "Normal Path", "AIF_RX"}, + + {"DAC In Mux", "Sgen", "SGEN DL"}, + {"SGEN DL", NULL, "SGEN DL SRC"}, + {"SGEN DL", NULL, "SGEN MUTE"}, + {"SGEN DL", NULL, "SGEN DL Enable"}, + {"SGEN DL", NULL, "DL Digital Clock"}, + + {"DACL", NULL, "DAC In Mux"}, + {"DACL", NULL, "DL Power Supply"}, + {"DACL", NULL, "DACL_BIASGEN"}, + + {"DACR", NULL, "DAC In Mux"}, + {"DACR", NULL, "DL Power Supply"}, + {"DACR", NULL, "DACR_BIASGEN"}, + + {"LOL Mux", "Playback", "DACL"}, + + {"LOL Buffer", NULL, "LOL Mux"}, + {"LOL Buffer", NULL, "LO Stability Enh"}, + {"LOL Buffer", NULL, "LOL Bias Gen"}, + + {"LINEOUT L", NULL, "LOL Buffer"}, + + /* Headphone Path */ + {"HPL Mux", "Audio Playback", "DACL"}, + {"HPR Mux", "Audio Playback", "DACR"}, + + {"HPL Mux", "LoudSPK Playback", "DACL"}, + {"HPR Mux", "LoudSPK Playback", "DACR"}, + + {"HPL Power", NULL, "HPL Mux"}, + {"HPR Power", NULL, "HPR Mux"}, + + {"Headphone L", NULL, "HPL Power"}, + {"Headphone R", NULL, "HPR Power"}, + + /* Receiver Path */ + {"RCV Mux", "Voice Playback", "DACL"}, + + {"RCV Buffer", NULL, "RCV Mux"}, + {"RCV Buffer", NULL, "RCV Stability Enh"}, + {"RCV Buffer", NULL, "RCV Bias Gen"}, + + {"Receiver", NULL, "RCV Buffer"}, +}; + +static int mt6351_codec_init_reg(struct snd_soc_component *cmpnt) +{ + int ret = 0; + + /* Disable CLKSQ 26MHz */ + regmap_update_bits(cmpnt->regmap, MT6351_TOP_CLKSQ, 0x0001, 0x0); + /* disable AUDGLB */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON9, + 0x1000, 0x1000); + /* Turn off AUDNCP_CLKDIV engine clock,Turn off AUD 26M */ + regmap_update_bits(cmpnt->regmap, MT6351_TOP_CKPDN_CON0_SET, + 0x3800, 0x3800); + /* Disable HeadphoneL/HeadphoneR/voice short circuit protection */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0, + 0xe000, 0xe000); + /* [5] = 1, disable LO buffer left short circuit protection */ + regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON3, + 0x20, 0x20); + /* Reverse the PMIC clock*/ + regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2, + 0x8000, 0x8000); + return ret; +} + +static int mt6351_codec_probe(struct snd_soc_component *cmpnt) +{ + struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); + + snd_soc_component_init_regmap(cmpnt, priv->regmap); + + mt6351_codec_init_reg(cmpnt); + return 0; +} + +static const struct snd_soc_component_driver mt6351_soc_component_driver = { + .probe = mt6351_codec_probe, + .controls = mt6351_snd_controls, + .num_controls = ARRAY_SIZE(mt6351_snd_controls), + .dapm_widgets = mt6351_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(mt6351_dapm_widgets), + .dapm_routes = mt6351_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(mt6351_dapm_routes), +}; + +static int mt6351_codec_driver_probe(struct platform_device *pdev) +{ + struct mt6351_priv *priv; + + priv = devm_kzalloc(&pdev->dev, + sizeof(struct mt6351_priv), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev_set_drvdata(&pdev->dev, priv); + + priv->dev = &pdev->dev; + + priv->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!priv->regmap) + return -ENODEV; + + dev_dbg(priv->dev, "%s(), dev name %s\n", + __func__, dev_name(&pdev->dev)); + + return devm_snd_soc_register_component(&pdev->dev, + &mt6351_soc_component_driver, + mt6351_dai_driver, + ARRAY_SIZE(mt6351_dai_driver)); +} + +static const struct of_device_id mt6351_of_match[] = { + {.compatible = "mediatek,mt6351-sound",}, + {} +}; + +static struct platform_driver mt6351_codec_driver = { + .driver = { + .name = "mt6351-sound", + .of_match_table = mt6351_of_match, + }, + .probe = mt6351_codec_driver_probe, +}; + +module_platform_driver(mt6351_codec_driver) + +/* Module information */ +MODULE_DESCRIPTION("MT6351 ALSA SoC codec driver"); +MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/mt6351.h b/sound/soc/codecs/mt6351.h new file mode 100644 index 000000000000..04b2ab694ec7 --- /dev/null +++ b/sound/soc/codecs/mt6351.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * mt6351.h -- mt6351 ALSA SoC audio codec driver + * + * Copyright (c) 2018 MediaTek Inc. + * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> + */ + +#ifndef __MT6351_H__ +#define __MT6351_H__ + +#define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000) +#define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002) +#define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004) +#define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006) +#define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008) +#define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a) +#define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c) +#define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e) +#define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010) +#define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012) +#define MT6351_AUDIO_TOP_CON0 (0x2000 + 0x0014) +#define MT6351_AFE_DL_SRC_MON0 (0x2000 + 0x0016) +#define MT6351_AFE_DL_SDM_TEST0 (0x2000 + 0x0018) +#define MT6351_AFE_MON_DEBUG0 (0x2000 + 0x001a) +#define MT6351_AFUNC_AUD_CON0 (0x2000 + 0x001c) +#define MT6351_AFUNC_AUD_CON1 (0x2000 + 0x001e) +#define MT6351_AFUNC_AUD_CON2 (0x2000 + 0x0020) +#define MT6351_AFUNC_AUD_CON3 (0x2000 + 0x0022) +#define MT6351_AFUNC_AUD_CON4 (0x2000 + 0x0024) +#define MT6351_AFUNC_AUD_MON0 (0x2000 + 0x0026) +#define MT6351_AFUNC_AUD_MON1 (0x2000 + 0x0028) +#define MT6351_AFE_UP8X_FIFO_CFG0 (0x2000 + 0x002c) +#define MT6351_AFE_UP8X_FIFO_LOG_MON0 (0x2000 + 0x002e) +#define MT6351_AFE_UP8X_FIFO_LOG_MON1 (0x2000 + 0x0030) +#define MT6351_AFE_DL_DC_COMP_CFG0 (0x2000 + 0x0032) +#define MT6351_AFE_DL_DC_COMP_CFG1 (0x2000 + 0x0034) +#define MT6351_AFE_DL_DC_COMP_CFG2 (0x2000 + 0x0036) +#define MT6351_AFE_PMIC_NEWIF_CFG0 (0x2000 + 0x0038) +#define MT6351_AFE_PMIC_NEWIF_CFG1 (0x2000 + 0x003a) +#define MT6351_AFE_PMIC_NEWIF_CFG2 (0x2000 + 0x003c) +#define MT6351_AFE_PMIC_NEWIF_CFG3 (0x2000 + 0x003e) +#define MT6351_AFE_SGEN_CFG0 (0x2000 + 0x0040) +#define MT6351_AFE_SGEN_CFG1 (0x2000 + 0x0042) +#define MT6351_AFE_ADDA2_UP8X_FIFO_LOG_MON0 (0x2000 + 0x004c) +#define MT6351_AFE_ADDA2_UP8X_FIFO_LOG_MON1 (0x2000 + 0x004e) +#define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG0 (0x2000 + 0x0050) +#define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG1 (0x2000 + 0x0052) +#define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG2 (0x2000 + 0x0054) +#define MT6351_AFE_DCCLK_CFG0 (0x2000 + 0x0090) +#define MT6351_AFE_DCCLK_CFG1 (0x2000 + 0x0092) +#define MT6351_AFE_HPANC_CFG0 (0x2000 + 0x0094) +#define MT6351_AFE_NCP_CFG0 (0x2000 + 0x0096) +#define MT6351_AFE_NCP_CFG1 (0x2000 + 0x0098) + +#define MT6351_TOP_CKPDN_CON0 0x023A +#define MT6351_TOP_CKPDN_CON0_SET 0x023C +#define MT6351_TOP_CKPDN_CON0_CLR 0x023E + +#define MT6351_TOP_CLKSQ 0x029A +#define MT6351_TOP_CLKSQ_SET 0x029C +#define MT6351_TOP_CLKSQ_CLR 0x029E + +#define MT6351_ZCD_CON0 0x0800 +#define MT6351_ZCD_CON1 0x0802 +#define MT6351_ZCD_CON2 0x0804 +#define MT6351_ZCD_CON3 0x0806 +#define MT6351_ZCD_CON4 0x0808 +#define MT6351_ZCD_CON5 0x080A + +#define MT6351_LDO_VA18_CON0 0x0A00 +#define MT6351_LDO_VA18_CON1 0x0A02 +#define MT6351_LDO_VUSB33_CON0 0x0A16 +#define MT6351_LDO_VUSB33_CON1 0x0A18 + +#define MT6351_AUDDEC_ANA_CON0 0x0CF2 +#define MT6351_AUDDEC_ANA_CON1 0x0CF4 +#define MT6351_AUDDEC_ANA_CON2 0x0CF6 +#define MT6351_AUDDEC_ANA_CON3 0x0CF8 +#define MT6351_AUDDEC_ANA_CON4 0x0CFA +#define MT6351_AUDDEC_ANA_CON5 0x0CFC +#define MT6351_AUDDEC_ANA_CON6 0x0CFE +#define MT6351_AUDDEC_ANA_CON7 0x0D00 +#define MT6351_AUDDEC_ANA_CON8 0x0D02 +#define MT6351_AUDDEC_ANA_CON9 0x0D04 +#define MT6351_AUDDEC_ANA_CON10 0x0D06 + +#define MT6351_AUDENC_ANA_CON0 0x0D08 +#define MT6351_AUDENC_ANA_CON1 0x0D0A +#define MT6351_AUDENC_ANA_CON2 0x0D0C +#define MT6351_AUDENC_ANA_CON3 0x0D0E +#define MT6351_AUDENC_ANA_CON4 0x0D10 +#define MT6351_AUDENC_ANA_CON5 0x0D12 +#define MT6351_AUDENC_ANA_CON6 0x0D14 +#define MT6351_AUDENC_ANA_CON7 0x0D16 +#define MT6351_AUDENC_ANA_CON8 0x0D18 +#define MT6351_AUDENC_ANA_CON9 0x0D1A +#define MT6351_AUDENC_ANA_CON10 0x0D1C +#define MT6351_AUDENC_ANA_CON11 0x0D1E +#define MT6351_AUDENC_ANA_CON12 0x0D20 +#define MT6351_AUDENC_ANA_CON13 0x0D22 +#define MT6351_AUDENC_ANA_CON14 0x0D24 +#define MT6351_AUDENC_ANA_CON15 0x0D26 +#define MT6351_AUDENC_ANA_CON16 0x0D28 +#endif diff --git a/sound/soc/codecs/nau8810.c b/sound/soc/codecs/nau8810.c index ca2ba1c7bb9a..bfd74b86c9d2 100644 --- a/sound/soc/codecs/nau8810.c +++ b/sound/soc/codecs/nau8810.c @@ -373,9 +373,11 @@ static const struct snd_kcontrol_new nau8810_mono_mixer_controls[] = { }; /* PGA Mute */ -static const struct snd_kcontrol_new nau8810_inpga_mute[] = { +static const struct snd_kcontrol_new nau8810_pgaboost_mixer_controls[] = { SOC_DAPM_SINGLE("PGA Mute Switch", NAU8810_REG_PGAGAIN, - NAU8810_PGAMT_SFT, 1, 0), + NAU8810_PGAMT_SFT, 1, 1), + SOC_DAPM_SINGLE("PMIC PGA Switch", NAU8810_REG_ADCBOOST, + NAU8810_PMICBSTGAIN_SFT, 0x7, 0), }; /* Input PGA */ @@ -386,11 +388,6 @@ static const struct snd_kcontrol_new nau8810_inpga[] = { NAU8810_PMICPGA_SFT, 1, 0), }; -/* Mic Input boost vol */ -static const struct snd_kcontrol_new nau8810_mic_boost_controls = - SOC_DAPM_SINGLE("Mic Volume", NAU8810_REG_ADCBOOST, - NAU8810_PMICBSTGAIN_SFT, 0x7, 0); - /* Loopback Switch */ static const struct snd_kcontrol_new nau8810_loopback = SOC_DAPM_SINGLE("Switch", NAU8810_REG_COMP, @@ -429,8 +426,8 @@ static const struct snd_soc_dapm_widget nau8810_dapm_widgets[] = { NAU8810_PGA_EN_SFT, 0, nau8810_inpga, ARRAY_SIZE(nau8810_inpga)), SND_SOC_DAPM_MIXER("Input Boost Stage", NAU8810_REG_POWER2, - NAU8810_BST_EN_SFT, 0, nau8810_inpga_mute, - ARRAY_SIZE(nau8810_inpga_mute)), + NAU8810_BST_EN_SFT, 0, nau8810_pgaboost_mixer_controls, + ARRAY_SIZE(nau8810_pgaboost_mixer_controls)), SND_SOC_DAPM_SUPPLY("Mic Bias", NAU8810_REG_POWER1, NAU8810_MICBIAS_EN_SFT, 0, NULL, 0), @@ -469,8 +466,8 @@ static const struct snd_soc_dapm_route nau8810_dapm_routes[] = { /* Input Boost Stage */ {"ADC", NULL, "Input Boost Stage"}, {"ADC", NULL, "PLL", check_mclk_select_pll}, - {"Input Boost Stage", NULL, "Input PGA"}, - {"Input Boost Stage", NULL, "MICP"}, + {"Input Boost Stage", "PGA Mute Switch", "Input PGA"}, + {"Input Boost Stage", "PMIC PGA Switch", "MICP"}, /* Input PGA */ {"Input PGA", NULL, "Mic Bias"}, diff --git a/sound/soc/codecs/nau8824.c b/sound/soc/codecs/nau8824.c index 637e9527805f..6bd14453f06e 100644 --- a/sound/soc/codecs/nau8824.c +++ b/sound/soc/codecs/nau8824.c @@ -205,11 +205,11 @@ static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout) if (timeout) { ret = down_timeout(&nau8824->jd_sem, timeout); if (ret < 0) - dev_warn(nau8824->dev, "Acquire semaphone timeout\n"); + dev_warn(nau8824->dev, "Acquire semaphore timeout\n"); } else { ret = down_interruptible(&nau8824->jd_sem); if (ret < 0) - dev_warn(nau8824->dev, "Acquire semaphone fail\n"); + dev_warn(nau8824->dev, "Acquire semaphore fail\n"); } return ret; @@ -409,6 +409,15 @@ static const struct snd_kcontrol_new nau8824_snd_controls[] = { SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0), SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0), + + SOC_SINGLE("THD for key media", + NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0), + SOC_SINGLE("THD for key voice command", + NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0), + SOC_SINGLE("THD for key volume up", + NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0), + SOC_SINGLE("THD for key volume down", + NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0), }; static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w, diff --git a/sound/soc/codecs/pcm1789.c b/sound/soc/codecs/pcm1789.c index 507ac9412d6c..21f15219b3ad 100644 --- a/sound/soc/codecs/pcm1789.c +++ b/sound/soc/codecs/pcm1789.c @@ -3,7 +3,7 @@ // Copyright (C) 2018 Bootlin // Mylène Josserand <mylene.josserand@bootlin.com> -#include <linux/gpio.h> +#include <linux/gpio/consumer.h> #include <linux/module.h> #include <linux/workqueue.h> diff --git a/sound/soc/codecs/pcm512x-i2c.c b/sound/soc/codecs/pcm512x-i2c.c index 5f9c069569d5..0fe5ced841a3 100644 --- a/sound/soc/codecs/pcm512x-i2c.c +++ b/sound/soc/codecs/pcm512x-i2c.c @@ -17,6 +17,7 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/i2c.h> +#include <linux/acpi.h> #include "pcm512x.h" @@ -52,6 +53,7 @@ static const struct i2c_device_id pcm512x_i2c_id[] = { }; MODULE_DEVICE_TABLE(i2c, pcm512x_i2c_id); +#if defined(CONFIG_OF) static const struct of_device_id pcm512x_of_match[] = { { .compatible = "ti,pcm5121", }, { .compatible = "ti,pcm5122", }, @@ -60,6 +62,18 @@ static const struct of_device_id pcm512x_of_match[] = { { } }; MODULE_DEVICE_TABLE(of, pcm512x_of_match); +#endif + +#ifdef CONFIG_ACPI +static const struct acpi_device_id pcm512x_acpi_match[] = { + { "104C5121", 0 }, + { "104C5122", 0 }, + { "104C5141", 0 }, + { "104C5142", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(acpi, pcm512x_acpi_match); +#endif static struct i2c_driver pcm512x_i2c_driver = { .probe = pcm512x_i2c_probe, @@ -67,7 +81,8 @@ static struct i2c_driver pcm512x_i2c_driver = { .id_table = pcm512x_i2c_id, .driver = { .name = "pcm512x", - .of_match_table = pcm512x_of_match, + .of_match_table = of_match_ptr(pcm512x_of_match), + .acpi_match_table = ACPI_PTR(pcm512x_acpi_match), .pm = &pcm512x_pm_ops, }, }; diff --git a/sound/soc/codecs/rt1305.c b/sound/soc/codecs/rt1305.c new file mode 100644 index 000000000000..f4c8c45f4010 --- /dev/null +++ b/sound/soc/codecs/rt1305.c @@ -0,0 +1,1191 @@ +/* + * rt1305.c -- RT1305 ALSA SoC amplifier component driver + * + * Copyright 2018 Realtek Semiconductor Corp. + * Author: Shuming Fan <shumingf@realtek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/acpi.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/regmap.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> +#include <linux/firmware.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> + +#include "rl6231.h" +#include "rt1305.h" + + +#define RT1305_PR_RANGE_BASE (0xff + 1) +#define RT1305_PR_SPACING 0x100 + +#define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING)) + + +static const struct regmap_range_cfg rt1305_ranges[] = { + { + .name = "PR", + .range_min = RT1305_PR_BASE, + .range_max = RT1305_PR_BASE + 0xff, + .selector_reg = RT1305_PRIV_INDEX, + .selector_mask = 0xff, + .selector_shift = 0x0, + .window_start = RT1305_PRIV_DATA, + .window_len = 0x1, + }, +}; + + +static const struct reg_sequence init_list[] = { + + { RT1305_PR_BASE + 0xcf, 0x5548 }, + { RT1305_PR_BASE + 0x5d, 0x0442 }, + { RT1305_PR_BASE + 0xc1, 0x0320 }, + + { RT1305_POWER_STATUS, 0x0000 }, + + { RT1305_SPK_TEMP_PROTECTION_1, 0xd6de }, + { RT1305_SPK_TEMP_PROTECTION_2, 0x0707 }, + { RT1305_SPK_TEMP_PROTECTION_3, 0x4090 }, + + { RT1305_DAC_SET_1, 0xdfdf }, /* 4 ohm 2W */ + { RT1305_ADC_SET_3, 0x0219 }, + { RT1305_ADC_SET_1, 0x170f }, /* 0.2 ohm RSense*/ + +}; +#define RT1305_INIT_REG_LEN ARRAY_SIZE(init_list) + +struct rt1305_priv { + struct snd_soc_component *component; + struct regmap *regmap; + + int sysclk; + int sysclk_src; + int lrck; + int bclk; + int master; + + int pll_src; + int pll_in; + int pll_out; +}; + +static const struct reg_default rt1305_reg[] = { + + { 0x04, 0x0400 }, + { 0x05, 0x0880 }, + { 0x06, 0x0000 }, + { 0x07, 0x3100 }, + { 0x08, 0x8000 }, + { 0x09, 0x0000 }, + { 0x0a, 0x087e }, + { 0x0b, 0x0020 }, + { 0x0c, 0x0802 }, + { 0x0d, 0x0020 }, + { 0x10, 0x1d1d }, + { 0x11, 0x1d1d }, + { 0x12, 0xffff }, + { 0x14, 0x000c }, + { 0x16, 0x1717 }, + { 0x17, 0x4000 }, + { 0x18, 0x0019 }, + { 0x20, 0x0000 }, + { 0x22, 0x0000 }, + { 0x24, 0x0000 }, + { 0x26, 0x0000 }, + { 0x28, 0x0000 }, + { 0x2a, 0x4000 }, + { 0x2b, 0x3000 }, + { 0x2d, 0x6000 }, + { 0x2e, 0x0000 }, + { 0x2f, 0x8000 }, + { 0x32, 0x0000 }, + { 0x39, 0x0001 }, + { 0x3a, 0x0000 }, + { 0x3b, 0x1020 }, + { 0x3c, 0x0000 }, + { 0x3d, 0x0000 }, + { 0x3e, 0x4c00 }, + { 0x3f, 0x3000 }, + { 0x40, 0x000c }, + { 0x42, 0x0400 }, + { 0x46, 0xc22c }, + { 0x47, 0x0000 }, + { 0x4b, 0x0000 }, + { 0x4c, 0x0300 }, + { 0x4f, 0xf000 }, + { 0x50, 0xc200 }, + { 0x51, 0x1f1f }, + { 0x52, 0x01f0 }, + { 0x53, 0x407f }, + { 0x54, 0xffff }, + { 0x58, 0x4005 }, + { 0x5e, 0x0000 }, + { 0x5f, 0x0000 }, + { 0x60, 0xee13 }, + { 0x62, 0x0000 }, + { 0x63, 0x5f5f }, + { 0x64, 0x0040 }, + { 0x65, 0x4000 }, + { 0x66, 0x4004 }, + { 0x67, 0x0306 }, + { 0x68, 0x8c04 }, + { 0x69, 0xe021 }, + { 0x6a, 0x0000 }, + { 0x6c, 0xaaaa }, + { 0x70, 0x0333 }, + { 0x71, 0x3330 }, + { 0x72, 0x3333 }, + { 0x73, 0x3300 }, + { 0x74, 0x0000 }, + { 0x75, 0x0000 }, + { 0x76, 0x0000 }, + { 0x7a, 0x0003 }, + { 0x7c, 0x10ec }, + { 0x7e, 0x6251 }, + { 0x80, 0x0800 }, + { 0x81, 0x4000 }, + { 0x82, 0x0000 }, + { 0x90, 0x7a01 }, + { 0x91, 0x8431 }, + { 0x92, 0x0180 }, + { 0x93, 0x0000 }, + { 0x94, 0x0000 }, + { 0x95, 0x0000 }, + { 0x96, 0x0000 }, + { 0x97, 0x0000 }, + { 0x98, 0x0000 }, + { 0x99, 0x0000 }, + { 0x9a, 0x0000 }, + { 0x9b, 0x0000 }, + { 0x9c, 0x0000 }, + { 0x9d, 0x0000 }, + { 0x9e, 0x0000 }, + { 0x9f, 0x0000 }, + { 0xa0, 0x0000 }, + { 0xb0, 0x8200 }, + { 0xb1, 0x00ff }, + { 0xb2, 0x0008 }, + { 0xc0, 0x0200 }, + { 0xc1, 0x0000 }, + { 0xc2, 0x0000 }, + { 0xc3, 0x0000 }, + { 0xc4, 0x0000 }, + { 0xc5, 0x0000 }, + { 0xc6, 0x0000 }, + { 0xc7, 0x0000 }, + { 0xc8, 0x0000 }, + { 0xc9, 0x0000 }, + { 0xca, 0x0200 }, + { 0xcb, 0x0000 }, + { 0xcc, 0x0000 }, + { 0xcd, 0x0000 }, + { 0xce, 0x0000 }, + { 0xcf, 0x0000 }, + { 0xd0, 0x0000 }, + { 0xd1, 0x0000 }, + { 0xd2, 0x0000 }, + { 0xd3, 0x0000 }, + { 0xd4, 0x0200 }, + { 0xd5, 0x0000 }, + { 0xd6, 0x0000 }, + { 0xd7, 0x0000 }, + { 0xd8, 0x0000 }, + { 0xd9, 0x0000 }, + { 0xda, 0x0000 }, + { 0xdb, 0x0000 }, + { 0xdc, 0x0000 }, + { 0xdd, 0x0000 }, + { 0xde, 0x0200 }, + { 0xdf, 0x0000 }, + { 0xe0, 0x0000 }, + { 0xe1, 0x0000 }, + { 0xe2, 0x0000 }, + { 0xe3, 0x0000 }, + { 0xe4, 0x0000 }, + { 0xe5, 0x0000 }, + { 0xe6, 0x0000 }, + { 0xe7, 0x0000 }, + { 0xe8, 0x0200 }, + { 0xe9, 0x0000 }, + { 0xea, 0x0000 }, + { 0xeb, 0x0000 }, + { 0xec, 0x0000 }, + { 0xed, 0x0000 }, + { 0xee, 0x0000 }, + { 0xef, 0x0000 }, + { 0xf0, 0x0000 }, + { 0xf1, 0x0000 }, + { 0xf2, 0x0200 }, + { 0xf3, 0x0000 }, + { 0xf4, 0x0000 }, + { 0xf5, 0x0000 }, + { 0xf6, 0x0000 }, + { 0xf7, 0x0000 }, + { 0xf8, 0x0000 }, + { 0xf9, 0x0000 }, + { 0xfa, 0x0000 }, + { 0xfb, 0x0000 }, +}; + +static int rt1305_reg_init(struct snd_soc_component *component) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN); + return 0; +} + +static bool rt1305_volatile_register(struct device *dev, unsigned int reg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) { + if (reg >= rt1305_ranges[i].range_min && + reg <= rt1305_ranges[i].range_max) { + return true; + } + } + + switch (reg) { + case RT1305_RESET: + case RT1305_SPDIF_IN_SET_1: + case RT1305_SPDIF_IN_SET_2: + case RT1305_SPDIF_IN_SET_3: + case RT1305_POWER_CTRL_2: + case RT1305_CLOCK_DETECT: + case RT1305_BIQUAD_SET_1: + case RT1305_BIQUAD_SET_2: + case RT1305_EQ_SET_2: + case RT1305_SPK_TEMP_PROTECTION_0: + case RT1305_SPK_TEMP_PROTECTION_2: + case RT1305_SPK_DC_DETECT_1: + case RT1305_SILENCE_DETECT: + case RT1305_VERSION_ID: + case RT1305_VENDOR_ID: + case RT1305_DEVICE_ID: + case RT1305_EFUSE_1: + case RT1305_EFUSE_3: + case RT1305_DC_CALIB_1: + case RT1305_DC_CALIB_3: + case RT1305_DAC_OFFSET_1: + case RT1305_DAC_OFFSET_2: + case RT1305_DAC_OFFSET_3: + case RT1305_DAC_OFFSET_4: + case RT1305_DAC_OFFSET_5: + case RT1305_DAC_OFFSET_6: + case RT1305_DAC_OFFSET_7: + case RT1305_DAC_OFFSET_8: + case RT1305_DAC_OFFSET_9: + case RT1305_DAC_OFFSET_10: + case RT1305_DAC_OFFSET_11: + case RT1305_TRIM_1: + case RT1305_TRIM_2: + return true; + + default: + return false; + } +} + +static bool rt1305_readable_register(struct device *dev, unsigned int reg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) { + if (reg >= rt1305_ranges[i].range_min && + reg <= rt1305_ranges[i].range_max) { + return true; + } + } + + switch (reg) { + case RT1305_RESET: + case RT1305_CLK_1 ... RT1305_CAL_EFUSE_CLOCK: + case RT1305_PLL0_1 ... RT1305_PLL1_2: + case RT1305_MIXER_CTRL_1: + case RT1305_MIXER_CTRL_2: + case RT1305_DAC_SET_1: + case RT1305_DAC_SET_2: + case RT1305_ADC_SET_1: + case RT1305_ADC_SET_2: + case RT1305_ADC_SET_3: + case RT1305_PATH_SET: + case RT1305_SPDIF_IN_SET_1: + case RT1305_SPDIF_IN_SET_2: + case RT1305_SPDIF_IN_SET_3: + case RT1305_SPDIF_OUT_SET_1: + case RT1305_SPDIF_OUT_SET_2: + case RT1305_SPDIF_OUT_SET_3: + case RT1305_I2S_SET_1: + case RT1305_I2S_SET_2: + case RT1305_PBTL_MONO_MODE_SRC: + case RT1305_MANUALLY_I2C_DEVICE: + case RT1305_POWER_STATUS: + case RT1305_POWER_CTRL_1: + case RT1305_POWER_CTRL_2: + case RT1305_POWER_CTRL_3: + case RT1305_POWER_CTRL_4: + case RT1305_POWER_CTRL_5: + case RT1305_CLOCK_DETECT: + case RT1305_BIQUAD_SET_1: + case RT1305_BIQUAD_SET_2: + case RT1305_ADJUSTED_HPF_1: + case RT1305_ADJUSTED_HPF_2: + case RT1305_EQ_SET_1: + case RT1305_EQ_SET_2: + case RT1305_SPK_TEMP_PROTECTION_0: + case RT1305_SPK_TEMP_PROTECTION_1: + case RT1305_SPK_TEMP_PROTECTION_2: + case RT1305_SPK_TEMP_PROTECTION_3: + case RT1305_SPK_DC_DETECT_1: + case RT1305_SPK_DC_DETECT_2: + case RT1305_LOUDNESS: + case RT1305_THERMAL_FOLD_BACK_1: + case RT1305_THERMAL_FOLD_BACK_2: + case RT1305_SILENCE_DETECT ... RT1305_SPK_EXCURSION_LIMITER_7: + case RT1305_VERSION_ID: + case RT1305_VENDOR_ID: + case RT1305_DEVICE_ID: + case RT1305_EFUSE_1: + case RT1305_EFUSE_2: + case RT1305_EFUSE_3: + case RT1305_DC_CALIB_1: + case RT1305_DC_CALIB_2: + case RT1305_DC_CALIB_3: + case RT1305_DAC_OFFSET_1 ... RT1305_DAC_OFFSET_14: + case RT1305_TRIM_1: + case RT1305_TRIM_2: + case RT1305_TUNE_INTERNAL_OSC: + case RT1305_BIQUAD1_H0_L_28_16 ... RT1305_BIQUAD3_A2_R_15_0: + return true; + default: + return false; + } +} + +static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0); + +static const char * const rt1305_rx_data_ch_select[] = { + "LR", + "RL", + "Copy L", + "Copy R", +}; + +static SOC_ENUM_SINGLE_DECL(rt1305_rx_data_ch_enum, RT1305_I2S_SET_2, 2, + rt1305_rx_data_ch_select); + +static void rt1305_reset(struct regmap *regmap) +{ + regmap_write(regmap, RT1305_RESET, 0); +} + +static const struct snd_kcontrol_new rt1305_snd_controls[] = { + SOC_DOUBLE_TLV("DAC Playback Volume", RT1305_DAC_SET_1, + 8, 0, 0xff, 0, dac_vol_tlv), + + /* I2S Data Channel Selection */ + SOC_ENUM("RX Channel Select", rt1305_rx_data_ch_enum), +}; + +static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(source->dapm); + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + unsigned int val; + + snd_soc_component_read(component, RT1305_CLK_1, &val); + + if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 && + (val & RT1305_SEL_PLL_SRC_2_RCCLK)) + return 1; + else + return 0; +} + +static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(source->dapm); + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1) + return 1; + else + return 0; +} + +static int rt1305_classd_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1, + RT1305_POW_PDB_JD_MASK, RT1305_POW_PDB_JD); + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1, + RT1305_POW_PDB_JD_MASK, 0); + usleep_range(150000, 200000); + break; + + default: + return 0; + } + + return 0; +} + +static const struct snd_kcontrol_new rt1305_sto_dac_l = + SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2, + RT1305_DVOL_MUTE_L_EN_SFT, 1, 1); + +static const struct snd_kcontrol_new rt1305_sto_dac_r = + SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2, + RT1305_DVOL_MUTE_R_EN_SFT, 1, 1); + +static const struct snd_soc_dapm_widget rt1305_dapm_widgets[] = { + SND_SOC_DAPM_SUPPLY("PLL0", RT1305_POWER_CTRL_1, + RT1305_POW_PLL0_EN_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PLL1", RT1305_POWER_CTRL_1, + RT1305_POW_PLL1_EN_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MBIAS", RT1305_POWER_CTRL_1, + RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1305_POWER_CTRL_1, + RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("LDO2", RT1305_POWER_CTRL_1, + RT1305_POW_LDO2_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BG2", RT1305_POWER_CTRL_1, + RT1305_POW_BG2_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("LDO2 IB2", RT1305_POWER_CTRL_1, + RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1, + RT1305_POW_VREF_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VREF1", RT1305_POWER_CTRL_1, + RT1305_POW_VREF1_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VREF2", RT1305_POWER_CTRL_1, + RT1305_POW_VREF2_BIT, 0, NULL, 0), + + + SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2, + RT1305_POW_DISC_VREF_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2, + RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2, + RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CHOP DAC", RT1305_POWER_CTRL_2, + RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1305_POWER_CTRL_2, + RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLAMP", RT1305_POWER_CTRL_2, + RT1305_POW_CLAMP_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BUFL", RT1305_POWER_CTRL_2, + RT1305_POW_BUFL_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BUFR", RT1305_POWER_CTRL_2, + RT1305_POW_BUFR_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CKGEN ADC", RT1305_POWER_CTRL_2, + RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC3 L", RT1305_POWER_CTRL_2, + RT1305_POW_ADC3_L_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC3 R", RT1305_POWER_CTRL_2, + RT1305_POW_ADC3_R_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("TRIOSC", RT1305_POWER_CTRL_2, + RT1305_POW_TRIOSC_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("AVDD1", RT1305_POWER_CTRL_2, + RT1305_POR_AVDD1_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("AVDD2", RT1305_POWER_CTRL_2, + RT1305_POR_AVDD2_BIT, 0, NULL, 0), + + + SND_SOC_DAPM_SUPPLY("VSENSE R", RT1305_POWER_CTRL_3, + RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VSENSE L", RT1305_POWER_CTRL_3, + RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ISENSE R", RT1305_POWER_CTRL_3, + RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ISENSE L", RT1305_POWER_CTRL_3, + RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("POR AVDD1", RT1305_POWER_CTRL_3, + RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("POR AVDD2", RT1305_POWER_CTRL_3, + RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VCM 6172", RT1305_POWER_CTRL_3, + RT1305_EN_VCM_6172_BIT, 0, NULL, 0), + + + /* Audio Interface */ + SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + + /* Digital Interface */ + SND_SOC_DAPM_SUPPLY("DAC L Power", RT1305_POWER_CTRL_2, + RT1305_POW_DAC1_L_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAC R Power", RT1305_POWER_CTRL_2, + RT1305_POW_DAC1_R_BIT, 0, NULL, 0), + SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l), + SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r), + + /* Output Lines */ + SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, + rt1305_classd_event, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_OUTPUT("SPOL"), + SND_SOC_DAPM_OUTPUT("SPOR"), +}; + +static const struct snd_soc_dapm_route rt1305_dapm_routes[] = { + + { "DAC", NULL, "AIF1RX" }, + + { "DAC", NULL, "PLL0", rt1305_is_rc_clk_from_pll }, + { "DAC", NULL, "PLL1", rt1305_is_sys_clk_from_pll }, + + { "DAC", NULL, "MBIAS" }, + { "DAC", NULL, "BG MBIAS" }, + { "DAC", NULL, "LDO2" }, + { "DAC", NULL, "BG2" }, + { "DAC", NULL, "LDO2 IB2" }, + { "DAC", NULL, "VREF" }, + { "DAC", NULL, "VREF1" }, + { "DAC", NULL, "VREF2" }, + + { "DAC", NULL, "DISC VREF" }, + { "DAC", NULL, "FASTB VREF" }, + { "DAC", NULL, "ULTRA FAST VREF" }, + { "DAC", NULL, "CHOP DAC" }, + { "DAC", NULL, "CKGEN DAC" }, + { "DAC", NULL, "CLAMP" }, + { "DAC", NULL, "CKGEN ADC" }, + { "DAC", NULL, "TRIOSC" }, + { "DAC", NULL, "AVDD1" }, + { "DAC", NULL, "AVDD2" }, + + { "DAC", NULL, "POR AVDD1" }, + { "DAC", NULL, "POR AVDD2" }, + { "DAC", NULL, "VCM 6172" }, + + { "DAC L", "Switch", "DAC" }, + { "DAC R", "Switch", "DAC" }, + + { "DAC R", NULL, "VSENSE R" }, + { "DAC L", NULL, "VSENSE L" }, + { "DAC R", NULL, "ISENSE R" }, + { "DAC L", NULL, "ISENSE L" }, + { "DAC L", NULL, "ADC3 L" }, + { "DAC R", NULL, "ADC3 R" }, + { "DAC L", NULL, "BUFL" }, + { "DAC R", NULL, "BUFR" }, + { "DAC L", NULL, "DAC L Power" }, + { "DAC R", NULL, "DAC R Power" }, + + { "CLASS D", NULL, "DAC L" }, + { "CLASS D", NULL, "DAC R" }, + + { "SPOL", NULL, "CLASS D" }, + { "SPOR", NULL, "CLASS D" }, +}; + +static int rt1305_get_clk_info(int sclk, int rate) +{ + int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16}; + + if (sclk <= 0 || rate <= 0) + return -EINVAL; + + rate = rate << 8; + for (i = 0; i < ARRAY_SIZE(pd); i++) + if (sclk == rate * pd[i]) + return i; + + return -EINVAL; +} + +static int rt1305_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + unsigned int val_len = 0, val_clk, mask_clk; + int pre_div, bclk_ms, frame_size; + + rt1305->lrck = params_rate(params); + pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck); + if (pre_div < 0) { + dev_warn(component->dev, "Force using PLL "); + snd_soc_dai_set_pll(dai, 0, RT1305_PLL1_S_BCLK, + rt1305->lrck * 64, rt1305->lrck * 256); + snd_soc_dai_set_sysclk(dai, RT1305_FS_SYS_PRE_S_PLL1, + rt1305->lrck * 256, SND_SOC_CLOCK_IN); + pre_div = 0; + } + frame_size = snd_soc_params_to_frame_size(params); + if (frame_size < 0) { + dev_err(component->dev, "Unsupported frame size: %d\n", + frame_size); + return -EINVAL; + } + + bclk_ms = frame_size > 32; + rt1305->bclk = rt1305->lrck * (32 << bclk_ms); + + dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", + bclk_ms, pre_div, dai->id); + + dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", + rt1305->lrck, pre_div, dai->id); + + switch (params_width(params)) { + case 16: + val_len |= RT1305_I2S_DL_SEL_16B; + break; + case 20: + val_len |= RT1305_I2S_DL_SEL_20B; + break; + case 24: + val_len |= RT1305_I2S_DL_SEL_24B; + break; + case 8: + val_len |= RT1305_I2S_DL_SEL_8B; + break; + default: + return -EINVAL; + } + + switch (dai->id) { + case RT1305_AIF1: + mask_clk = RT1305_DIV_FS_SYS_MASK; + val_clk = pre_div << RT1305_DIV_FS_SYS_SFT; + snd_soc_component_update_bits(component, RT1305_I2S_SET_2, + RT1305_I2S_DL_SEL_MASK, + val_len); + break; + default: + dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); + return -EINVAL; + } + + snd_soc_component_update_bits(component, RT1305_CLK_2, + mask_clk, val_clk); + + return 0; +} + +static int rt1305_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_component *component = dai->component; + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + unsigned int reg_val = 0, reg1_val = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + reg_val |= RT1305_SEL_I2S_OUT_MODE_M; + rt1305->master = 1; + break; + case SND_SOC_DAIFMT_CBS_CFS: + reg_val |= RT1305_SEL_I2S_OUT_MODE_S; + rt1305->master = 0; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + reg1_val |= RT1305_I2S_BCLK_INV; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + break; + case SND_SOC_DAIFMT_LEFT_J: + reg1_val |= RT1305_I2S_DF_SEL_LEFT; + break; + case SND_SOC_DAIFMT_DSP_A: + reg1_val |= RT1305_I2S_DF_SEL_PCM_A; + break; + case SND_SOC_DAIFMT_DSP_B: + reg1_val |= RT1305_I2S_DF_SEL_PCM_B; + break; + default: + return -EINVAL; + } + + switch (dai->id) { + case RT1305_AIF1: + snd_soc_component_update_bits(component, RT1305_I2S_SET_1, + RT1305_SEL_I2S_OUT_MODE_MASK, reg_val); + snd_soc_component_update_bits(component, RT1305_I2S_SET_2, + RT1305_I2S_DF_SEL_MASK | RT1305_I2S_BCLK_MASK, + reg1_val); + break; + default: + dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); + return -EINVAL; + } + return 0; +} + +static int rt1305_set_component_sysclk(struct snd_soc_component *component, + int clk_id, int source, unsigned int freq, int dir) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + unsigned int reg_val = 0; + + if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src) + return 0; + + switch (clk_id) { + case RT1305_FS_SYS_PRE_S_MCLK: + reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK; + snd_soc_component_update_bits(component, + RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK, + RT1305_SEL_CLK_DET_SRC_MCLK); + break; + case RT1305_FS_SYS_PRE_S_PLL1: + reg_val |= RT1305_SEL_FS_SYS_PRE_PLL; + break; + case RT1305_FS_SYS_PRE_S_RCCLK: + reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK; + break; + default: + dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); + return -EINVAL; + } + snd_soc_component_update_bits(component, RT1305_CLK_1, + RT1305_SEL_FS_SYS_PRE_MASK, reg_val); + rt1305->sysclk = freq; + rt1305->sysclk_src = clk_id; + + dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", + freq, clk_id); + + return 0; +} + +static int rt1305_set_component_pll(struct snd_soc_component *component, + int pll_id, int source, unsigned int freq_in, + unsigned int freq_out) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + struct rl6231_pll_code pll_code; + int ret; + + if (source == rt1305->pll_src && freq_in == rt1305->pll_in && + freq_out == rt1305->pll_out) + return 0; + + if (!freq_in || !freq_out) { + dev_dbg(component->dev, "PLL disabled\n"); + + rt1305->pll_in = 0; + rt1305->pll_out = 0; + snd_soc_component_update_bits(component, RT1305_CLK_1, + RT1305_SEL_FS_SYS_PRE_MASK | RT1305_SEL_PLL_SRC_1_MASK, + RT1305_SEL_FS_SYS_PRE_PLL | RT1305_SEL_PLL_SRC_1_BCLK); + return 0; + } + + switch (source) { + case RT1305_PLL2_S_MCLK: + snd_soc_component_update_bits(component, RT1305_CLK_1, + RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK | + RT1305_DIV_PLL_SRC_2_MASK, + RT1305_SEL_PLL_SRC_2_MCLK | RT1305_SEL_PLL_SRC_1_PLL2); + snd_soc_component_update_bits(component, + RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK, + RT1305_SEL_CLK_DET_SRC_MCLK); + break; + case RT1305_PLL1_S_BCLK: + snd_soc_component_update_bits(component, + RT1305_CLK_1, RT1305_SEL_PLL_SRC_1_MASK, + RT1305_SEL_PLL_SRC_1_BCLK); + break; + case RT1305_PLL2_S_RCCLK: + snd_soc_component_update_bits(component, RT1305_CLK_1, + RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK | + RT1305_DIV_PLL_SRC_2_MASK, + RT1305_SEL_PLL_SRC_2_RCCLK | RT1305_SEL_PLL_SRC_1_PLL2); + freq_in = 98304000; + break; + default: + dev_err(component->dev, "Unknown PLL Source %d\n", source); + return -EINVAL; + } + + ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); + if (ret < 0) { + dev_err(component->dev, "Unsupport input clock %d\n", freq_in); + return ret; + } + + dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", + pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), + pll_code.n_code, pll_code.k_code); + + snd_soc_component_write(component, RT1305_PLL1_1, + (pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT | + pll_code.m_bp << RT1305_PLL_1_M_BYPASS_SFT | + pll_code.n_code); + snd_soc_component_write(component, RT1305_PLL1_2, + pll_code.k_code); + + rt1305->pll_in = freq_in; + rt1305->pll_out = freq_out; + rt1305->pll_src = source; + + return 0; +} + +static int rt1305_probe(struct snd_soc_component *component) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + rt1305->component = component; + + /* initial settings */ + rt1305_reg_init(component); + + return 0; +} + +static void rt1305_remove(struct snd_soc_component *component) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + rt1305_reset(rt1305->regmap); +} + +#ifdef CONFIG_PM +static int rt1305_suspend(struct snd_soc_component *component) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + regcache_cache_only(rt1305->regmap, true); + regcache_mark_dirty(rt1305->regmap); + + return 0; +} + +static int rt1305_resume(struct snd_soc_component *component) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + regcache_cache_only(rt1305->regmap, false); + regcache_sync(rt1305->regmap); + + return 0; +} +#else +#define rt1305_suspend NULL +#define rt1305_resume NULL +#endif + +#define RT1305_STEREO_RATES SNDRV_PCM_RATE_8000_192000 +#define RT1305_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ + SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +static const struct snd_soc_dai_ops rt1305_aif_dai_ops = { + .hw_params = rt1305_hw_params, + .set_fmt = rt1305_set_dai_fmt, +}; + +static struct snd_soc_dai_driver rt1305_dai[] = { + { + .name = "rt1305-aif", + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT1305_STEREO_RATES, + .formats = RT1305_FORMATS, + }, + .ops = &rt1305_aif_dai_ops, + }, +}; + +static const struct snd_soc_component_driver soc_component_dev_rt1305 = { + .probe = rt1305_probe, + .remove = rt1305_remove, + .suspend = rt1305_suspend, + .resume = rt1305_resume, + .controls = rt1305_snd_controls, + .num_controls = ARRAY_SIZE(rt1305_snd_controls), + .dapm_widgets = rt1305_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rt1305_dapm_widgets), + .dapm_routes = rt1305_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rt1305_dapm_routes), + .set_sysclk = rt1305_set_component_sysclk, + .set_pll = rt1305_set_component_pll, + .use_pmdown_time = 1, + .endianness = 1, + .non_legacy_dai_naming = 1, +}; + +static const struct regmap_config rt1305_regmap = { + .reg_bits = 8, + .val_bits = 16, + .max_register = RT1305_MAX_REG + 1 + (ARRAY_SIZE(rt1305_ranges) * + RT1305_PR_SPACING), + .volatile_reg = rt1305_volatile_register, + .readable_reg = rt1305_readable_register, + .cache_type = REGCACHE_RBTREE, + .reg_defaults = rt1305_reg, + .num_reg_defaults = ARRAY_SIZE(rt1305_reg), + .ranges = rt1305_ranges, + .num_ranges = ARRAY_SIZE(rt1305_ranges), + .use_single_rw = true, +}; + +#if defined(CONFIG_OF) +static const struct of_device_id rt1305_of_match[] = { + { .compatible = "realtek,rt1305", }, + { .compatible = "realtek,rt1306", }, + {}, +}; +MODULE_DEVICE_TABLE(of, rt1305_of_match); +#endif + +#ifdef CONFIG_ACPI +static struct acpi_device_id rt1305_acpi_match[] = { + {"10EC1305", 0,}, + {"10EC1306", 0,}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, rt1305_acpi_match); +#endif + +static const struct i2c_device_id rt1305_i2c_id[] = { + { "rt1305", 0 }, + { "rt1306", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, rt1305_i2c_id); + +static void rt1305_calibrate(struct rt1305_priv *rt1305) +{ + unsigned int valmsb, vallsb, offsetl, offsetr; + unsigned int rh, rl, rhl, r0ohm; + u64 r0l, r0r; + + regcache_cache_bypass(rt1305->regmap, true); + + rt1305_reset(rt1305->regmap); + regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320); + regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000); + regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0); + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080); + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe); + + /* Sin Gen */ + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442); + + regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320); + regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0); + + /* EFUSE read */ + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080); + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000); + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000); + + regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb); + regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb); + offsetl = valmsb << 16 | vallsb; + regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb); + regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb); + offsetr = valmsb << 16 | vallsb; + pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr); + + /* R0 calibration */ + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe); + regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13); + regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650); + + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c); + regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80); + msleep(2000); + regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh); + regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl); + rhl = (rh << 16) | rl; + r0ohm = (rhl*10) / 33554432; + + pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl); + pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10)); + + r0l = 562949953421312; + if (rhl != 0) + do_div(r0l, rhl); + pr_debug("Left_r0 = 0x%llx\n", r0l); + + regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80); + msleep(2000); + regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh); + regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl); + rhl = (rh << 16) | rl; + r0ohm = (rhl*10) / 33554432; + + pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl); + pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10)); + + r0r = 562949953421312; + if (rhl != 0) + do_div(r0r, rhl); + pr_debug("Right_r0 = 0x%llx\n", r0r); + + regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec); + + if ((r0l > R0_UPPER) && (r0l < R0_LOWER) && + (r0r > R0_UPPER) && (r0r < R0_LOWER)) { + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e, + (r0l >> 16) & 0xffff); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f, + r0l & 0xffff); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe, + ((r0r >> 16) & 0xffff) | 0xf800); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd, + r0r & 0xffff); + } else { + pr_err("R0 calibration failed\n"); + } + + /* restore some registers */ + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe); + usleep_range(200000, 400000); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442); + regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000); + regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000); + regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000); + + regcache_cache_bypass(rt1305->regmap, false); +} + +static int rt1305_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct rt1305_priv *rt1305; + int ret; + unsigned int val; + + rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv), + GFP_KERNEL); + if (rt1305 == NULL) + return -ENOMEM; + + i2c_set_clientdata(i2c, rt1305); + + rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap); + if (IS_ERR(rt1305->regmap)) { + ret = PTR_ERR(rt1305->regmap); + dev_err(&i2c->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val); + if (val != RT1305_DEVICE_ID_NUM) { + dev_err(&i2c->dev, + "Device with ID register %x is not rt1305\n", val); + return -ENODEV; + } + + rt1305_reset(rt1305->regmap); + rt1305_calibrate(rt1305); + + return snd_soc_register_component(&i2c->dev, &soc_component_dev_rt1305, + rt1305_dai, ARRAY_SIZE(rt1305_dai)); +} + +static int rt1305_i2c_remove(struct i2c_client *i2c) +{ + snd_soc_unregister_component(&i2c->dev); + + return 0; +} + +static void rt1305_i2c_shutdown(struct i2c_client *client) +{ + struct rt1305_priv *rt1305 = i2c_get_clientdata(client); + + rt1305_reset(rt1305->regmap); +} + + +static struct i2c_driver rt1305_i2c_driver = { + .driver = { + .name = "rt1305", +#if defined(CONFIG_OF) + .of_match_table = rt1305_of_match, +#endif +#if defined(CONFIG_ACPI) + .acpi_match_table = ACPI_PTR(rt1305_acpi_match) +#endif + }, + .probe = rt1305_i2c_probe, + .remove = rt1305_i2c_remove, + .shutdown = rt1305_i2c_shutdown, + .id_table = rt1305_i2c_id, +}; +module_i2c_driver(rt1305_i2c_driver); + +MODULE_DESCRIPTION("ASoC RT1305 amplifier driver"); +MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/rt1305.h b/sound/soc/codecs/rt1305.h new file mode 100644 index 000000000000..bde86f97729a --- /dev/null +++ b/sound/soc/codecs/rt1305.h @@ -0,0 +1,276 @@ +/* + * RT1305.h -- RT1305 ALSA SoC amplifier component driver + * + * Copyright 2018 Realtek Semiconductor Corp. + * Author: Shuming Fan <shumingf@realtek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _RT1305_H_ +#define _RT1305_H_ + +#define RT1305_DEVICE_ID_NUM 0x6251 + +#define RT1305_RESET 0x00 +#define RT1305_CLK_1 0x04 +#define RT1305_CLK_2 0x05 +#define RT1305_CLK_3 0x06 +#define RT1305_DFLL_REG 0x07 +#define RT1305_CAL_EFUSE_CLOCK 0x08 +#define RT1305_PLL0_1 0x0a +#define RT1305_PLL0_2 0x0b +#define RT1305_PLL1_1 0x0c +#define RT1305_PLL1_2 0x0d +#define RT1305_MIXER_CTRL_1 0x10 +#define RT1305_MIXER_CTRL_2 0x11 +#define RT1305_DAC_SET_1 0x12 +#define RT1305_DAC_SET_2 0x14 +#define RT1305_ADC_SET_1 0x16 +#define RT1305_ADC_SET_2 0x17 +#define RT1305_ADC_SET_3 0x18 +#define RT1305_PATH_SET 0x20 +#define RT1305_SPDIF_IN_SET_1 0x22 +#define RT1305_SPDIF_IN_SET_2 0x24 +#define RT1305_SPDIF_IN_SET_3 0x26 +#define RT1305_SPDIF_OUT_SET_1 0x28 +#define RT1305_SPDIF_OUT_SET_2 0x2a +#define RT1305_SPDIF_OUT_SET_3 0x2b +#define RT1305_I2S_SET_1 0x2d +#define RT1305_I2S_SET_2 0x2e +#define RT1305_PBTL_MONO_MODE_SRC 0x2f +#define RT1305_MANUALLY_I2C_DEVICE 0x32 +#define RT1305_POWER_STATUS 0x39 +#define RT1305_POWER_CTRL_1 0x3a +#define RT1305_POWER_CTRL_2 0x3b +#define RT1305_POWER_CTRL_3 0x3c +#define RT1305_POWER_CTRL_4 0x3d +#define RT1305_POWER_CTRL_5 0x3e +#define RT1305_CLOCK_DETECT 0x3f +#define RT1305_BIQUAD_SET_1 0x40 +#define RT1305_BIQUAD_SET_2 0x42 +#define RT1305_ADJUSTED_HPF_1 0x46 +#define RT1305_ADJUSTED_HPF_2 0x47 +#define RT1305_EQ_SET_1 0x4b +#define RT1305_EQ_SET_2 0x4c +#define RT1305_SPK_TEMP_PROTECTION_0 0x4f +#define RT1305_SPK_TEMP_PROTECTION_1 0x50 +#define RT1305_SPK_TEMP_PROTECTION_2 0x51 +#define RT1305_SPK_TEMP_PROTECTION_3 0x52 +#define RT1305_SPK_DC_DETECT_1 0x53 +#define RT1305_SPK_DC_DETECT_2 0x54 +#define RT1305_LOUDNESS 0x58 +#define RT1305_THERMAL_FOLD_BACK_1 0x5e +#define RT1305_THERMAL_FOLD_BACK_2 0x5f +#define RT1305_SILENCE_DETECT 0x60 +#define RT1305_ALC_DRC_1 0x62 +#define RT1305_ALC_DRC_2 0x63 +#define RT1305_ALC_DRC_3 0x64 +#define RT1305_ALC_DRC_4 0x65 +#define RT1305_PRIV_INDEX 0x6a +#define RT1305_PRIV_DATA 0x6c +#define RT1305_SPK_EXCURSION_LIMITER_7 0x76 +#define RT1305_VERSION_ID 0x7a +#define RT1305_VENDOR_ID 0x7c +#define RT1305_DEVICE_ID 0x7e +#define RT1305_EFUSE_1 0x80 +#define RT1305_EFUSE_2 0x81 +#define RT1305_EFUSE_3 0x82 +#define RT1305_DC_CALIB_1 0x90 +#define RT1305_DC_CALIB_2 0x91 +#define RT1305_DC_CALIB_3 0x92 +#define RT1305_DAC_OFFSET_1 0x93 +#define RT1305_DAC_OFFSET_2 0x94 +#define RT1305_DAC_OFFSET_3 0x95 +#define RT1305_DAC_OFFSET_4 0x96 +#define RT1305_DAC_OFFSET_5 0x97 +#define RT1305_DAC_OFFSET_6 0x98 +#define RT1305_DAC_OFFSET_7 0x99 +#define RT1305_DAC_OFFSET_8 0x9a +#define RT1305_DAC_OFFSET_9 0x9b +#define RT1305_DAC_OFFSET_10 0x9c +#define RT1305_DAC_OFFSET_11 0x9d +#define RT1305_DAC_OFFSET_12 0x9e +#define RT1305_DAC_OFFSET_13 0x9f +#define RT1305_DAC_OFFSET_14 0xa0 +#define RT1305_TRIM_1 0xb0 +#define RT1305_TRIM_2 0xb1 +#define RT1305_TUNE_INTERNAL_OSC 0xb2 +#define RT1305_BIQUAD1_H0_L_28_16 0xc0 +#define RT1305_BIQUAD3_A2_R_15_0 0xfb +#define RT1305_MAX_REG 0xff + +/* CLOCK-1 (0x04) */ +#define RT1305_SEL_PLL_SRC_2_MASK (0x1 << 15) +#define RT1305_SEL_PLL_SRC_2_SFT 15 +#define RT1305_SEL_PLL_SRC_2_MCLK (0x0 << 15) +#define RT1305_SEL_PLL_SRC_2_RCCLK (0x1 << 15) +#define RT1305_DIV_PLL_SRC_2_MASK (0x3 << 13) +#define RT1305_DIV_PLL_SRC_2_SFT 13 +#define RT1305_SEL_PLL_SRC_1_MASK (0x3 << 10) +#define RT1305_SEL_PLL_SRC_1_SFT 10 +#define RT1305_SEL_PLL_SRC_1_PLL2 (0x0 << 10) +#define RT1305_SEL_PLL_SRC_1_BCLK (0x1 << 10) +#define RT1305_SEL_PLL_SRC_1_DFLL (0x2 << 10) +#define RT1305_SEL_FS_SYS_PRE_MASK (0x3 << 8) +#define RT1305_SEL_FS_SYS_PRE_SFT 8 +#define RT1305_SEL_FS_SYS_PRE_MCLK (0x0 << 8) +#define RT1305_SEL_FS_SYS_PRE_PLL (0x1 << 8) +#define RT1305_SEL_FS_SYS_PRE_RCCLK (0x2 << 8) +#define RT1305_DIV_FS_SYS_MASK (0x7 << 4) +#define RT1305_DIV_FS_SYS_SFT 4 + +/* PLL1M/N/K Code-1 (0x0c) */ +#define RT1305_PLL_1_M_SFT 12 +#define RT1305_PLL_1_M_BYPASS_MASK (0x1 << 11) +#define RT1305_PLL_1_M_BYPASS_SFT 11 +#define RT1305_PLL_1_M_BYPASS (0x1 << 11) +#define RT1305_PLL_1_N_MASK (0x1ff << 0) + +/* DAC Setting (0x14) */ +#define RT1305_DVOL_MUTE_L_EN_SFT 15 +#define RT1305_DVOL_MUTE_R_EN_SFT 14 + +/* I2S Setting-1 (0x2d) */ +#define RT1305_SEL_I2S_OUT_MODE_MASK (0x1 << 15) +#define RT1305_SEL_I2S_OUT_MODE_SFT 15 +#define RT1305_SEL_I2S_OUT_MODE_S (0x0 << 15) +#define RT1305_SEL_I2S_OUT_MODE_M (0x1 << 15) + +/* I2S Setting-2 (0x2e) */ +#define RT1305_I2S_DF_SEL_MASK (0x3 << 12) +#define RT1305_I2S_DF_SEL_SFT 12 +#define RT1305_I2S_DF_SEL_I2S (0x0 << 12) +#define RT1305_I2S_DF_SEL_LEFT (0x1 << 12) +#define RT1305_I2S_DF_SEL_PCM_A (0x2 << 12) +#define RT1305_I2S_DF_SEL_PCM_B (0x3 << 12) +#define RT1305_I2S_DL_SEL_MASK (0x3 << 10) +#define RT1305_I2S_DL_SEL_SFT 10 +#define RT1305_I2S_DL_SEL_16B (0x0 << 10) +#define RT1305_I2S_DL_SEL_20B (0x1 << 10) +#define RT1305_I2S_DL_SEL_24B (0x2 << 10) +#define RT1305_I2S_DL_SEL_8B (0x3 << 10) +#define RT1305_I2S_BCLK_MASK (0x1 << 9) +#define RT1305_I2S_BCLK_SFT 9 +#define RT1305_I2S_BCLK_NORMAL (0x0 << 9) +#define RT1305_I2S_BCLK_INV (0x1 << 9) + +/* Power Control-1 (0x3a) */ +#define RT1305_POW_PDB_JD_MASK (0x1 << 12) +#define RT1305_POW_PDB_JD (0x1 << 12) +#define RT1305_POW_PDB_JD_BIT 12 +#define RT1305_POW_PLL0_EN (0x1 << 11) +#define RT1305_POW_PLL0_EN_BIT 11 +#define RT1305_POW_PLL1_EN (0x1 << 10) +#define RT1305_POW_PLL1_EN_BIT 10 +#define RT1305_POW_PDB_JD_POLARITY (0x1 << 9) +#define RT1305_POW_PDB_JD_POLARITY_BIT 9 +#define RT1305_POW_MBIAS_LV (0x1 << 8) +#define RT1305_POW_MBIAS_LV_BIT 8 +#define RT1305_POW_BG_MBIAS_LV (0x1 << 7) +#define RT1305_POW_BG_MBIAS_LV_BIT 7 +#define RT1305_POW_LDO2 (0x1 << 6) +#define RT1305_POW_LDO2_BIT 6 +#define RT1305_POW_BG2 (0x1 << 5) +#define RT1305_POW_BG2_BIT 5 +#define RT1305_POW_LDO2_IB2 (0x1 << 4) +#define RT1305_POW_LDO2_IB2_BIT 4 +#define RT1305_POW_VREF (0x1 << 3) +#define RT1305_POW_VREF_BIT 3 +#define RT1305_POW_VREF1 (0x1 << 2) +#define RT1305_POW_VREF1_BIT 2 +#define RT1305_POW_VREF2 (0x1 << 1) +#define RT1305_POW_VREF2_BIT 1 + +/* Power Control-2 (0x3b) */ +#define RT1305_POW_DISC_VREF (1 << 15) +#define RT1305_POW_DISC_VREF_BIT 15 +#define RT1305_POW_FASTB_VREF (1 << 14) +#define RT1305_POW_FASTB_VREF_BIT 14 +#define RT1305_POW_ULTRA_FAST_VREF (1 << 13) +#define RT1305_POW_ULTRA_FAST_VREF_BIT 13 +#define RT1305_POW_CKXEN_DAC (1 << 12) +#define RT1305_POW_CKXEN_DAC_BIT 12 +#define RT1305_POW_EN_CKGEN_DAC (1 << 11) +#define RT1305_POW_EN_CKGEN_DAC_BIT 11 +#define RT1305_POW_DAC1_L (1 << 10) +#define RT1305_POW_DAC1_L_BIT 10 +#define RT1305_POW_DAC1_R (1 << 9) +#define RT1305_POW_DAC1_R_BIT 9 +#define RT1305_POW_CLAMP (1 << 8) +#define RT1305_POW_CLAMP_BIT 8 +#define RT1305_POW_BUFL (1 << 7) +#define RT1305_POW_BUFL_BIT 7 +#define RT1305_POW_BUFR (1 << 6) +#define RT1305_POW_BUFR_BIT 6 +#define RT1305_POW_EN_CKGEN_ADC (1 << 5) +#define RT1305_POW_EN_CKGEN_ADC_BIT 5 +#define RT1305_POW_ADC3_L (1 << 4) +#define RT1305_POW_ADC3_L_BIT 4 +#define RT1305_POW_ADC3_R (1 << 3) +#define RT1305_POW_ADC3_R_BIT 3 +#define RT1305_POW_TRIOSC (1 << 2) +#define RT1305_POW_TRIOSC_BIT 2 +#define RT1305_POR_AVDD1 (1 << 1) +#define RT1305_POR_AVDD1_BIT 1 +#define RT1305_POR_AVDD2 (1 << 0) +#define RT1305_POR_AVDD2_BIT 0 + +/* Power Control-3 (0x3c) */ +#define RT1305_POW_VSENSE_RCH (1 << 15) +#define RT1305_POW_VSENSE_RCH_BIT 15 +#define RT1305_POW_VSENSE_LCH (1 << 14) +#define RT1305_POW_VSENSE_LCH_BIT 14 +#define RT1305_POW_ISENSE_RCH (1 << 13) +#define RT1305_POW_ISENSE_RCH_BIT 13 +#define RT1305_POW_ISENSE_LCH (1 << 12) +#define RT1305_POW_ISENSE_LCH_BIT 12 +#define RT1305_POW_POR_AVDD1 (1 << 11) +#define RT1305_POW_POR_AVDD1_BIT 11 +#define RT1305_POW_POR_AVDD2 (1 << 10) +#define RT1305_POW_POR_AVDD2_BIT 10 +#define RT1305_EN_K_HV (1 << 9) +#define RT1305_EN_K_HV_BIT 9 +#define RT1305_EN_PRE_K_HV (1 << 8) +#define RT1305_EN_PRE_K_HV_BIT 8 +#define RT1305_EN_EFUSE_1P8V (1 << 7) +#define RT1305_EN_EFUSE_1P8V_BIT 7 +#define RT1305_EN_EFUSE_5V (1 << 6) +#define RT1305_EN_EFUSE_5V_BIT 6 +#define RT1305_EN_VCM_6172 (1 << 5) +#define RT1305_EN_VCM_6172_BIT 5 +#define RT1305_POR_EFUSE (1 << 4) +#define RT1305_POR_EFUSE_BIT 4 + +/* Clock Detect (0x3f) */ +#define RT1305_SEL_CLK_DET_SRC_MASK (0x1 << 12) +#define RT1305_SEL_CLK_DET_SRC_SFT 12 +#define RT1305_SEL_CLK_DET_SRC_MCLK (0x0 << 12) +#define RT1305_SEL_CLK_DET_SRC_BCLK (0x1 << 12) + + +/* System Clock Source */ +enum { + RT1305_FS_SYS_PRE_S_MCLK, + RT1305_FS_SYS_PRE_S_PLL1, + RT1305_FS_SYS_PRE_S_RCCLK, /* 98.304M Hz */ +}; + +/* PLL Source 1/2 */ +enum { + RT1305_PLL1_S_BCLK, + RT1305_PLL2_S_MCLK, + RT1305_PLL2_S_RCCLK, /* 98.304M Hz */ +}; + +enum { + RT1305_AIF1, + RT1305_AIFS +}; + +#define R0_UPPER 0x2E8BA2 //5.5 ohm +#define R0_LOWER 0x666666 //2.5 ohm + +#endif /* end of _RT1305_H_ */ diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c index 05567426f211..8bf8d360c25f 100644 --- a/sound/soc/codecs/rt5640.c +++ b/sound/soc/codecs/rt5640.c @@ -24,6 +24,7 @@ #include <linux/spi/spi.h> #include <linux/acpi.h> #include <sound/core.h> +#include <sound/jack.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/soc.h> @@ -476,20 +477,6 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w, return idx; } -static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, - struct snd_soc_dapm_widget *sink) -{ - struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); - unsigned int val; - - val = snd_soc_component_read32(component, RT5640_GLB_CLK); - val &= RT5640_SCLK_SRC_MASK; - if (val == RT5640_SCLK_SRC_PLL1) - return 1; - else - return 0; -} - static int is_using_asrc(struct snd_soc_dapm_widget *source, struct snd_soc_dapm_widget *sink) { @@ -1071,9 +1058,6 @@ static int rt5640_hp_post_event(struct snd_soc_dapm_widget *w, } static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = { - SND_SOC_DAPM_SUPPLY("PLL1", RT5640_PWR_ANLG2, - RT5640_PWR_PLL_BIT, 0, NULL, 0), - /* ASRC */ SND_SOC_DAPM_SUPPLY_S("Stereo Filter ASRC", 1, RT5640_ASRC_1, 15, 0, NULL, 0), @@ -1427,22 +1411,18 @@ static const struct snd_soc_dapm_route rt5640_dapm_routes[] = { {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"}, {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"}, {"Stereo ADC MIXL", NULL, "Stereo Filter"}, - {"Stereo Filter", NULL, "PLL1", is_sys_clk_from_pll}, {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"}, {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"}, {"Stereo ADC MIXR", NULL, "Stereo Filter"}, - {"Stereo Filter", NULL, "PLL1", is_sys_clk_from_pll}, {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"}, {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"}, {"Mono ADC MIXL", NULL, "Mono Left Filter"}, - {"Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll}, {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"}, {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"}, {"Mono ADC MIXR", NULL, "Mono Right Filter"}, - {"Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll}, {"IF2 ADC L", NULL, "Mono ADC MIXL"}, {"IF2 ADC R", NULL, "Mono ADC MIXR"}, @@ -1512,10 +1492,8 @@ static const struct snd_soc_dapm_route rt5640_dapm_routes[] = { {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"}, {"DAC L1", NULL, "Stereo DAC MIXL"}, - {"DAC L1", NULL, "PLL1", is_sys_clk_from_pll}, {"DAC L1", NULL, "DAC L1 Power"}, {"DAC R1", NULL, "Stereo DAC MIXR"}, - {"DAC R1", NULL, "PLL1", is_sys_clk_from_pll}, {"DAC R1", NULL, "DAC R1 Power"}, {"SPK MIXL", "REC MIXL Switch", "RECMIXL"}, @@ -1622,10 +1600,8 @@ static const struct snd_soc_dapm_route rt5640_specific_dapm_routes[] = { {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"}, {"DAC L2", NULL, "Mono DAC MIXL"}, - {"DAC L2", NULL, "PLL1", is_sys_clk_from_pll}, {"DAC L2", NULL, "DAC L2 Power"}, {"DAC R2", NULL, "Mono DAC MIXR"}, - {"DAC R2", NULL, "PLL1", is_sys_clk_from_pll}, {"DAC R2", NULL, "DAC R2 Power"}, {"SPK MIXL", "DAC L2 Switch", "DAC L2"}, @@ -1861,6 +1837,7 @@ static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai, struct snd_soc_component *component = dai->component; struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component); unsigned int reg_val = 0; + unsigned int pll_bit = 0; if (freq == rt5640->sysclk && clk_id == rt5640->sysclk_src) return 0; @@ -1871,6 +1848,7 @@ static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai, break; case RT5640_SCLK_S_PLL1: reg_val |= RT5640_SCLK_SRC_PLL1; + pll_bit |= RT5640_PWR_PLL; break; case RT5640_SCLK_S_RCCLK: reg_val |= RT5640_SCLK_SRC_RCCLK; @@ -1879,6 +1857,8 @@ static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai, dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); return -EINVAL; } + snd_soc_component_update_bits(component, RT5640_PWR_ANLG2, + RT5640_PWR_PLL, pll_bit); snd_soc_component_update_bits(component, RT5640_GLB_CLK, RT5640_SCLK_SRC_MASK, reg_val); rt5640->sysclk = freq; @@ -2114,10 +2094,376 @@ int rt5640_sel_asrc_clk_src(struct snd_soc_component *component, } EXPORT_SYMBOL_GPL(rt5640_sel_asrc_clk_src); +static void rt5640_enable_micbias1_for_ovcd(struct snd_soc_component *component) +{ + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + + snd_soc_dapm_mutex_lock(dapm); + snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2"); + snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS1"); + /* OVCD is unreliable when used with RCCLK as sysclk-source */ + snd_soc_dapm_force_enable_pin_unlocked(dapm, "Platform Clock"); + snd_soc_dapm_sync_unlocked(dapm); + snd_soc_dapm_mutex_unlock(dapm); +} + +static void rt5640_disable_micbias1_for_ovcd(struct snd_soc_component *component) +{ + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + + snd_soc_dapm_mutex_lock(dapm); + snd_soc_dapm_disable_pin_unlocked(dapm, "Platform Clock"); + snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS1"); + snd_soc_dapm_disable_pin_unlocked(dapm, "LDO2"); + snd_soc_dapm_sync_unlocked(dapm); + snd_soc_dapm_mutex_unlock(dapm); +} + +static void rt5640_enable_micbias1_ovcd_irq(struct snd_soc_component *component) +{ + struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component); + + snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2, + RT5640_IRQ_MB1_OC_MASK, RT5640_IRQ_MB1_OC_NOR); + rt5640->ovcd_irq_enabled = true; +} + +static void rt5640_disable_micbias1_ovcd_irq(struct snd_soc_component *component) +{ + struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component); + + snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2, + RT5640_IRQ_MB1_OC_MASK, RT5640_IRQ_MB1_OC_BP); + rt5640->ovcd_irq_enabled = false; +} + +static void rt5640_clear_micbias1_ovcd(struct snd_soc_component *component) +{ + snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2, + RT5640_MB1_OC_STATUS, 0); +} + +static bool rt5640_micbias1_ovcd(struct snd_soc_component *component) +{ + int val; + + val = snd_soc_component_read32(component, RT5640_IRQ_CTRL2); + dev_dbg(component->dev, "irq ctrl2 %#04x\n", val); + + return (val & RT5640_MB1_OC_STATUS); +} + +static bool rt5640_jack_inserted(struct snd_soc_component *component) +{ + struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component); + int val; + + val = snd_soc_component_read32(component, RT5640_INT_IRQ_ST); + dev_dbg(component->dev, "irq status %#04x\n", val); + + if (rt5640->jd_inverted) + return !(val & RT5640_JD_STATUS); + else + return (val & RT5640_JD_STATUS); +} + +/* Jack detect and button-press timings */ +#define JACK_SETTLE_TIME 100 /* milli seconds */ +#define JACK_DETECT_COUNT 5 +#define JACK_DETECT_MAXCOUNT 20 /* Aprox. 2 seconds worth of tries */ +#define JACK_UNPLUG_TIME 80 /* milli seconds */ +#define BP_POLL_TIME 10 /* milli seconds */ +#define BP_POLL_MAXCOUNT 200 /* assume something is wrong after this */ +#define BP_THRESHOLD 3 + +static void rt5640_start_button_press_work(struct snd_soc_component *component) +{ + struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component); + + rt5640->poll_count = 0; + rt5640->press_count = 0; + rt5640->release_count = 0; + rt5640->pressed = false; + rt5640->press_reported = false; + rt5640_clear_micbias1_ovcd(component); + schedule_delayed_work(&rt5640->bp_work, msecs_to_jiffies(BP_POLL_TIME)); +} + +static void rt5640_button_press_work(struct work_struct *work) +{ + struct rt5640_priv *rt5640 = + container_of(work, struct rt5640_priv, bp_work.work); + struct snd_soc_component *component = rt5640->component; + + /* Check the jack was not removed underneath us */ + if (!rt5640_jack_inserted(component)) + return; + + if (rt5640_micbias1_ovcd(component)) { + rt5640->release_count = 0; + rt5640->press_count++; + /* Remember till after JACK_UNPLUG_TIME wait */ + if (rt5640->press_count >= BP_THRESHOLD) + rt5640->pressed = true; + rt5640_clear_micbias1_ovcd(component); + } else { + rt5640->press_count = 0; + rt5640->release_count++; + } + + /* + * The pins get temporarily shorted on jack unplug, so we poll for + * at least JACK_UNPLUG_TIME milli-seconds before reporting a press. + */ + rt5640->poll_count++; + if (rt5640->poll_count < (JACK_UNPLUG_TIME / BP_POLL_TIME)) { + schedule_delayed_work(&rt5640->bp_work, + msecs_to_jiffies(BP_POLL_TIME)); + return; + } + + if (rt5640->pressed && !rt5640->press_reported) { + dev_dbg(component->dev, "headset button press\n"); + snd_soc_jack_report(rt5640->jack, SND_JACK_BTN_0, + SND_JACK_BTN_0); + rt5640->press_reported = true; + } + + if (rt5640->release_count >= BP_THRESHOLD) { + if (rt5640->press_reported) { + dev_dbg(component->dev, "headset button release\n"); + snd_soc_jack_report(rt5640->jack, 0, SND_JACK_BTN_0); + } + /* Re-enable OVCD IRQ to detect next press */ + rt5640_enable_micbias1_ovcd_irq(component); + return; /* Stop polling */ + } + + schedule_delayed_work(&rt5640->bp_work, msecs_to_jiffies(BP_POLL_TIME)); +} + +static int rt5640_detect_headset(struct snd_soc_component *component) +{ + int i, headset_count = 0, headphone_count = 0; + + /* + * We get the insertion event before the jack is fully inserted at which + * point the second ring on a TRRS connector may short the 2nd ring and + * sleeve contacts, also the overcurrent detection is not entirely + * reliable. So we try several times with a wait in between until we + * detect the same type JACK_DETECT_COUNT times in a row. + */ + for (i = 0; i < JACK_DETECT_MAXCOUNT; i++) { + /* Clear any previous over-current status flag */ + rt5640_clear_micbias1_ovcd(component); + + msleep(JACK_SETTLE_TIME); + + /* Check the jack is still connected before checking ovcd */ + if (!rt5640_jack_inserted(component)) + return 0; + + if (rt5640_micbias1_ovcd(component)) { + /* + * Over current detected, there is a short between the + * 2nd ring contact and the ground, so a TRS connector + * without a mic contact and thus plain headphones. + */ + dev_dbg(component->dev, "jack mic-gnd shorted\n"); + headset_count = 0; + headphone_count++; + if (headphone_count == JACK_DETECT_COUNT) + return SND_JACK_HEADPHONE; + } else { + dev_dbg(component->dev, "jack mic-gnd open\n"); + headphone_count = 0; + headset_count++; + if (headset_count == JACK_DETECT_COUNT) + return SND_JACK_HEADSET; + } + } + + dev_err(component->dev, "Error detecting headset vs headphones, bad contact?, assuming headphones\n"); + return SND_JACK_HEADPHONE; +} + +static void rt5640_jack_work(struct work_struct *work) +{ + struct rt5640_priv *rt5640 = + container_of(work, struct rt5640_priv, jack_work); + struct snd_soc_component *component = rt5640->component; + int status; + + if (!rt5640_jack_inserted(component)) { + /* Jack removed, or spurious IRQ? */ + if (rt5640->jack->status & SND_JACK_HEADPHONE) { + if (rt5640->jack->status & SND_JACK_MICROPHONE) { + cancel_delayed_work_sync(&rt5640->bp_work); + rt5640_disable_micbias1_ovcd_irq(component); + rt5640_disable_micbias1_for_ovcd(component); + } + snd_soc_jack_report(rt5640->jack, 0, + SND_JACK_HEADSET | SND_JACK_BTN_0); + dev_dbg(component->dev, "jack unplugged\n"); + } + } else if (!(rt5640->jack->status & SND_JACK_HEADPHONE)) { + /* Jack inserted */ + WARN_ON(rt5640->ovcd_irq_enabled); + rt5640_enable_micbias1_for_ovcd(component); + status = rt5640_detect_headset(component); + if (status == SND_JACK_HEADSET) { + /* Enable ovcd IRQ for button press detect. */ + rt5640_enable_micbias1_ovcd_irq(component); + } else { + /* No more need for overcurrent detect. */ + rt5640_disable_micbias1_for_ovcd(component); + } + dev_dbg(component->dev, "detect status %#02x\n", status); + snd_soc_jack_report(rt5640->jack, status, SND_JACK_HEADSET); + } else if (rt5640->ovcd_irq_enabled && rt5640_micbias1_ovcd(component)) { + dev_dbg(component->dev, "OVCD IRQ\n"); + + /* + * The ovcd IRQ keeps firing while the button is pressed, so + * we disable it and start polling the button until released. + * + * The disable will make the IRQ pin 0 again and since we get + * IRQs on both edges (so as to detect both jack plugin and + * unplug) this means we will immediately get another IRQ. + * The ovcd_irq_enabled check above makes the 2ND IRQ a NOP. + */ + rt5640_disable_micbias1_ovcd_irq(component); + rt5640_start_button_press_work(component); + + /* + * If the jack-detect IRQ flag goes high (unplug) after our + * above rt5640_jack_inserted() check and before we have + * disabled the OVCD IRQ, the IRQ pin will stay high and as + * we react to edges, we miss the unplug event -> recheck. + */ + queue_work(system_long_wq, &rt5640->jack_work); + } +} + +static irqreturn_t rt5640_irq(int irq, void *data) +{ + struct rt5640_priv *rt5640 = data; + + if (rt5640->jack) + queue_work(system_long_wq, &rt5640->jack_work); + + return IRQ_HANDLED; +} + +static void rt5640_cancel_work(void *data) +{ + struct rt5640_priv *rt5640 = data; + + cancel_work_sync(&rt5640->jack_work); + cancel_delayed_work_sync(&rt5640->bp_work); +} + +static void rt5640_enable_jack_detect(struct snd_soc_component *component, + struct snd_soc_jack *jack) +{ + struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component); + + /* Select JD-source */ + snd_soc_component_update_bits(component, RT5640_JD_CTRL, + RT5640_JD_MASK, rt5640->jd_src); + + /* Selecting GPIO01 as an interrupt */ + snd_soc_component_update_bits(component, RT5640_GPIO_CTRL1, + RT5640_GP1_PIN_MASK, RT5640_GP1_PIN_IRQ); + + /* Set GPIO1 output */ + snd_soc_component_update_bits(component, RT5640_GPIO_CTRL3, + RT5640_GP1_PF_MASK, RT5640_GP1_PF_OUT); + + /* Enabling jd2 in general control 1 */ + snd_soc_component_write(component, RT5640_DUMMY1, 0x3f41); + + /* Enabling jd2 in general control 2 */ + snd_soc_component_write(component, RT5640_DUMMY2, 0x4001); + + snd_soc_component_write(component, RT5640_PR_BASE + RT5640_BIAS_CUR4, + 0xa800 | rt5640->ovcd_sf); + + snd_soc_component_update_bits(component, RT5640_MICBIAS, + RT5640_MIC1_OVTH_MASK | RT5640_MIC1_OVCD_MASK, + rt5640->ovcd_th | RT5640_MIC1_OVCD_EN); + + /* + * The over-current-detect is only reliable in detecting the absence + * of over-current, when the mic-contact in the jack is short-circuited, + * the hardware periodically retries if it can apply the bias-current + * leading to the ovcd status flip-flopping 1-0-1 with it being 0 about + * 10% of the time, as we poll the ovcd status bit we might hit that + * 10%, so we enable sticky mode and when checking OVCD we clear the + * status, msleep() a bit and then check to get a reliable reading. + */ + snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2, + RT5640_MB1_OC_STKY_MASK, RT5640_MB1_OC_STKY_EN); + + /* + * All IRQs get or-ed together, so we need the jack IRQ to report 0 + * when a jack is inserted so that the OVCD IRQ then toggles the IRQ + * pin 0/1 instead of it being stuck to 1. So we invert the JD polarity + * on systems where the hardware does not already do this. + */ + if (rt5640->jd_inverted) + snd_soc_component_write(component, RT5640_IRQ_CTRL1, + RT5640_IRQ_JD_NOR); + else + snd_soc_component_write(component, RT5640_IRQ_CTRL1, + RT5640_IRQ_JD_NOR | RT5640_JD_P_INV); + + rt5640->jack = jack; + if (rt5640->jack->status & SND_JACK_MICROPHONE) { + rt5640_enable_micbias1_for_ovcd(component); + rt5640_enable_micbias1_ovcd_irq(component); + } + + enable_irq(rt5640->irq); + /* sync initial jack state */ + queue_work(system_long_wq, &rt5640->jack_work); +} + +static void rt5640_disable_jack_detect(struct snd_soc_component *component) +{ + struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component); + + disable_irq(rt5640->irq); + rt5640_cancel_work(rt5640); + + if (rt5640->jack->status & SND_JACK_MICROPHONE) { + rt5640_disable_micbias1_ovcd_irq(component); + rt5640_disable_micbias1_for_ovcd(component); + snd_soc_jack_report(rt5640->jack, 0, SND_JACK_BTN_0); + } + + rt5640->jack = NULL; +} + +static int rt5640_set_jack(struct snd_soc_component *component, + struct snd_soc_jack *jack, void *data) +{ + if (jack) + rt5640_enable_jack_detect(component, jack); + else + rt5640_disable_jack_detect(component); + + return 0; +} + static int rt5640_probe(struct snd_soc_component *component) { struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component); + u32 dmic1_data_pin = 0; + u32 dmic2_data_pin = 0; + bool dmic_en = false; + u32 val; /* Check if MCLK provided */ rt5640->mclk = devm_clk_get(component->dev, "mclk"); @@ -2159,9 +2505,86 @@ static int rt5640_probe(struct snd_soc_component *component) return -ENODEV; } - if (rt5640->pdata.dmic_en) - rt5640_dmic_enable(component, rt5640->pdata.dmic1_data_pin, - rt5640->pdata.dmic2_data_pin); + /* + * Note on some platforms the platform code may need to add device-props + * rather then relying only on properties set by the firmware. + * Therefor the property parsing MUST be done here, rather then from + * rt5640_i2c_probe(), so that the platform-code can attach extra + * properties before calling snd_soc_register_card(). + */ + if (device_property_read_bool(component->dev, "realtek,in1-differential")) + snd_soc_component_update_bits(component, RT5640_IN1_IN2, + RT5640_IN_DF1, RT5640_IN_DF1); + + if (device_property_read_bool(component->dev, "realtek,in2-differential")) + snd_soc_component_update_bits(component, RT5640_IN3_IN4, + RT5640_IN_DF2, RT5640_IN_DF2); + + if (device_property_read_bool(component->dev, "realtek,in3-differential")) + snd_soc_component_update_bits(component, RT5640_IN1_IN2, + RT5640_IN_DF2, RT5640_IN_DF2); + + if (device_property_read_u32(component->dev, "realtek,dmic1-data-pin", + &val) == 0 && val) { + dmic1_data_pin = val - 1; + dmic_en = true; + } + + if (device_property_read_u32(component->dev, "realtek,dmic2-data-pin", + &val) == 0 && val) { + dmic2_data_pin = val - 1; + dmic_en = true; + } + + if (dmic_en) + rt5640_dmic_enable(component, dmic1_data_pin, dmic2_data_pin); + + if (device_property_read_u32(component->dev, + "realtek,jack-detect-source", &val) == 0) { + if (val <= RT5640_JD_SRC_GPIO4) + rt5640->jd_src = val << RT5640_JD_SFT; + else + dev_warn(component->dev, "Warning: Invalid jack-detect-source value: %d, leaving jack-detect disabled\n", + val); + } + + if (!device_property_read_bool(component->dev, "realtek,jack-detect-not-inverted")) + rt5640->jd_inverted = true; + + /* + * Testing on various boards has shown that good defaults for the OVCD + * threshold and scale-factor are 2000µA and 0.75. For an effective + * limit of 1500µA, this seems to be more reliable then 1500µA and 1.0. + */ + rt5640->ovcd_th = RT5640_MIC1_OVTH_2000UA; + rt5640->ovcd_sf = RT5640_MIC_OVCD_SF_0P75; + + if (device_property_read_u32(component->dev, + "realtek,over-current-threshold-microamp", &val) == 0) { + switch (val) { + case 600: + rt5640->ovcd_th = RT5640_MIC1_OVTH_600UA; + break; + case 1500: + rt5640->ovcd_th = RT5640_MIC1_OVTH_1500UA; + break; + case 2000: + rt5640->ovcd_th = RT5640_MIC1_OVTH_2000UA; + break; + default: + dev_warn(component->dev, "Warning: Invalid over-current-threshold-microamp value: %d, defaulting to 2000uA\n", + val); + } + } + + if (device_property_read_u32(component->dev, + "realtek,over-current-scale-factor", &val) == 0) { + if (val <= RT5640_OVCD_SF_1P5) + rt5640->ovcd_sf = val << RT5640_MIC_OVCD_SF_SFT; + else + dev_warn(component->dev, "Warning: Invalid over-current-scale-factor value: %d, defaulting to 0.75\n", + val); + } return 0; } @@ -2180,8 +2603,8 @@ static int rt5640_suspend(struct snd_soc_component *component) rt5640_reset(component); regcache_cache_only(rt5640->regmap, true); regcache_mark_dirty(rt5640->regmap); - if (gpio_is_valid(rt5640->pdata.ldo1_en)) - gpio_set_value_cansleep(rt5640->pdata.ldo1_en, 0); + if (gpio_is_valid(rt5640->ldo1_en)) + gpio_set_value_cansleep(rt5640->ldo1_en, 0); return 0; } @@ -2190,8 +2613,8 @@ static int rt5640_resume(struct snd_soc_component *component) { struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component); - if (gpio_is_valid(rt5640->pdata.ldo1_en)) { - gpio_set_value_cansleep(rt5640->pdata.ldo1_en, 1); + if (gpio_is_valid(rt5640->ldo1_en)) { + gpio_set_value_cansleep(rt5640->ldo1_en, 1); msleep(400); } @@ -2263,6 +2686,7 @@ static const struct snd_soc_component_driver soc_component_dev_rt5640 = { .suspend = rt5640_suspend, .resume = rt5640_resume, .set_bias_level = rt5640_set_bias_level, + .set_jack = rt5640_set_jack, .controls = rt5640_snd_controls, .num_controls = ARRAY_SIZE(rt5640_snd_controls), .dapm_widgets = rt5640_dapm_widgets, @@ -2323,22 +2747,16 @@ MODULE_DEVICE_TABLE(acpi, rt5640_acpi_match); static int rt5640_parse_dt(struct rt5640_priv *rt5640, struct device_node *np) { - rt5640->pdata.in1_diff = of_property_read_bool(np, - "realtek,in1-differential"); - rt5640->pdata.in2_diff = of_property_read_bool(np, - "realtek,in2-differential"); - - rt5640->pdata.ldo1_en = of_get_named_gpio(np, - "realtek,ldo1-en-gpios", 0); + rt5640->ldo1_en = of_get_named_gpio(np, "realtek,ldo1-en-gpios", 0); /* * LDO1_EN is optional (it may be statically tied on the board). * -ENOENT means that the property doesn't exist, i.e. there is no * GPIO, so is not an error. Any other error code means the property * exists, but could not be parsed. */ - if (!gpio_is_valid(rt5640->pdata.ldo1_en) && - (rt5640->pdata.ldo1_en != -ENOENT)) - return rt5640->pdata.ldo1_en; + if (!gpio_is_valid(rt5640->ldo1_en) && + (rt5640->ldo1_en != -ENOENT)) + return rt5640->ldo1_en; return 0; } @@ -2346,7 +2764,6 @@ static int rt5640_parse_dt(struct rt5640_priv *rt5640, struct device_node *np) static int rt5640_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { - struct rt5640_platform_data *pdata = dev_get_platdata(&i2c->dev); struct rt5640_priv *rt5640; int ret; unsigned int val; @@ -2358,22 +2775,12 @@ static int rt5640_i2c_probe(struct i2c_client *i2c, return -ENOMEM; i2c_set_clientdata(i2c, rt5640); - if (pdata) { - rt5640->pdata = *pdata; - /* - * Translate zero'd out (default) pdata value to an invalid - * GPIO ID. This makes the pdata and DT paths consistent in - * terms of the value left in this field when no GPIO is - * specified, but means we can't actually use GPIO 0. - */ - if (!rt5640->pdata.ldo1_en) - rt5640->pdata.ldo1_en = -EINVAL; - } else if (i2c->dev.of_node) { + if (i2c->dev.of_node) { ret = rt5640_parse_dt(rt5640, i2c->dev.of_node); if (ret) return ret; } else - rt5640->pdata.ldo1_en = -EINVAL; + rt5640->ldo1_en = -EINVAL; rt5640->regmap = devm_regmap_init_i2c(i2c, &rt5640_regmap); if (IS_ERR(rt5640->regmap)) { @@ -2383,13 +2790,13 @@ static int rt5640_i2c_probe(struct i2c_client *i2c, return ret; } - if (gpio_is_valid(rt5640->pdata.ldo1_en)) { - ret = devm_gpio_request_one(&i2c->dev, rt5640->pdata.ldo1_en, + if (gpio_is_valid(rt5640->ldo1_en)) { + ret = devm_gpio_request_one(&i2c->dev, rt5640->ldo1_en, GPIOF_OUT_INIT_HIGH, "RT5640 LDO1_EN"); if (ret < 0) { dev_err(&i2c->dev, "Failed to request LDO1_EN %d: %d\n", - rt5640->pdata.ldo1_en, ret); + rt5640->ldo1_en, ret); return ret; } msleep(400); @@ -2412,19 +2819,27 @@ static int rt5640_i2c_probe(struct i2c_client *i2c, regmap_update_bits(rt5640->regmap, RT5640_DUMMY1, RT5640_MCLK_DET, RT5640_MCLK_DET); - if (rt5640->pdata.in1_diff) - regmap_update_bits(rt5640->regmap, RT5640_IN1_IN2, - RT5640_IN_DF1, RT5640_IN_DF1); - - if (rt5640->pdata.in2_diff) - regmap_update_bits(rt5640->regmap, RT5640_IN3_IN4, - RT5640_IN_DF2, RT5640_IN_DF2); + rt5640->hp_mute = 1; + rt5640->irq = i2c->irq; + INIT_DELAYED_WORK(&rt5640->bp_work, rt5640_button_press_work); + INIT_WORK(&rt5640->jack_work, rt5640_jack_work); - if (rt5640->pdata.in3_diff) - regmap_update_bits(rt5640->regmap, RT5640_IN1_IN2, - RT5640_IN_DF2, RT5640_IN_DF2); + /* Make sure work is stopped on probe-error / remove */ + ret = devm_add_action_or_reset(&i2c->dev, rt5640_cancel_work, rt5640); + if (ret) + return ret; - rt5640->hp_mute = 1; + ret = devm_request_irq(&i2c->dev, rt5640->irq, rt5640_irq, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING + | IRQF_ONESHOT, "rt5640", rt5640); + if (ret == 0) { + /* Gets re-enabled by rt5640_set_jack() */ + disable_irq(rt5640->irq); + } else { + dev_warn(&i2c->dev, "Failed to reguest IRQ %d: %d\n", + rt5640->irq, ret); + rt5640->irq = -ENXIO; + } return devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5640, diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h index c473e8ae2eda..e29e3e7d61b0 100644 --- a/sound/soc/codecs/rt5640.h +++ b/sound/soc/codecs/rt5640.h @@ -13,7 +13,8 @@ #define _RT5640_H #include <linux/clk.h> -#include <sound/rt5640.h> +#include <linux/workqueue.h> +#include <dt-bindings/sound/rt5640.h> /* Info */ #define RT5640_RESET 0x00 @@ -146,6 +147,7 @@ /* Index of Codec Private Register definition */ +#define RT5640_BIAS_CUR4 0x15 #define RT5640_CHPUMP_INT_REG1 0x24 #define RT5640_MAMP_INT_REG2 0x37 #define RT5640_3D_SPK 0x63 @@ -1607,10 +1609,17 @@ #define RT5640_MB2_OC_P_SFT 6 #define RT5640_MB2_OC_P_NOR (0x0 << 6) #define RT5640_MB2_OC_P_INV (0x1 << 6) -#define RT5640_MB1_OC_CLR (0x1 << 3) -#define RT5640_MB1_OC_CLR_SFT 3 -#define RT5640_MB2_OC_CLR (0x1 << 2) -#define RT5640_MB2_OC_CLR_SFT 2 +#define RT5640_MB1_OC_STATUS (0x1 << 3) +#define RT5640_MB1_OC_STATUS_SFT 3 +#define RT5640_MB2_OC_STATUS (0x1 << 2) +#define RT5640_MB2_OC_STATUS_SFT 2 + +/* GPIO and Internal Status (0xbf) */ +#define RT5640_GPIO1_STATUS (0x1 << 8) +#define RT5640_GPIO2_STATUS (0x1 << 7) +#define RT5640_JD_STATUS (0x1 << 4) +#define RT5640_OVT_STATUS (0x1 << 3) +#define RT5640_CLS_D_OVCD_STATUS (0x1 << 0) /* GPIO Control 1 (0xc0) */ #define RT5640_GP1_PIN_MASK (0x1 << 15) @@ -1978,6 +1987,15 @@ #define RT5640_MCLK_DET (0x1 << 11) /* Codec Private Register definition */ + +/* MIC Over current threshold scale factor (0x15) */ +#define RT5640_MIC_OVCD_SF_MASK (0x3 << 8) +#define RT5640_MIC_OVCD_SF_SFT 8 +#define RT5640_MIC_OVCD_SF_0P5 (0x0 << 8) +#define RT5640_MIC_OVCD_SF_0P75 (0x1 << 8) +#define RT5640_MIC_OVCD_SF_1P0 (0x2 << 8) +#define RT5640_MIC_OVCD_SF_1P5 (0x3 << 8) + /* 3D Speaker Control (0x63) */ #define RT5640_3D_SPK_MASK (0x1 << 15) #define RT5640_3D_SPK_SFT 15 @@ -2103,10 +2121,11 @@ enum { struct rt5640_priv { struct snd_soc_component *component; - struct rt5640_platform_data pdata; struct regmap *regmap; struct clk *mclk; + int ldo1_en; /* GPIO for LDO1_EN */ + int irq; int sysclk; int sysclk_src; int lrck[RT5640_AIFS]; @@ -2119,6 +2138,21 @@ struct rt5640_priv { bool hp_mute; bool asrc_en; + + /* Jack and button detect data */ + bool ovcd_irq_enabled; + bool pressed; + bool press_reported; + int press_count; + int release_count; + int poll_count; + struct delayed_work bp_work; + struct work_struct jack_work; + struct snd_soc_jack *jack; + unsigned int jd_src; + bool jd_inverted; + unsigned int ovcd_th; + unsigned int ovcd_sf; }; int rt5640_dmic_enable(struct snd_soc_component *component, diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c index bc8d829ce45b..712384581ebf 100644 --- a/sound/soc/codecs/rt5645.c +++ b/sound/soc/codecs/rt5645.c @@ -3652,6 +3652,11 @@ static const struct rt5645_platform_data asus_t100ha_platform_data = { .inv_jd1_1 = true, }; +static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = { + .jd_mode = 3, + .in2_diff = true, +}; + static const struct rt5645_platform_data jd_mode3_platform_data = { .jd_mode = 3, }; @@ -3735,6 +3740,24 @@ static const struct dmi_system_id dmi_platform_data[] = { }, .driver_data = (void *)&jd_mode3_platform_data, }, + { + .ident = "Lenovo Ideapad Miix 310", + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"), + DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"), + }, + .driver_data = (void *)&lenovo_ideapad_miix_310_pdata, + }, + { + .ident = "Lenovo Ideapad Miix 320", + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"), + DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"), + }, + .driver_data = (void *)&intel_braswell_platform_data, + }, { } }; diff --git a/sound/soc/codecs/rt5663.c b/sound/soc/codecs/rt5663.c index 20c0aeea6ca3..9bd24ad42240 100644 --- a/sound/soc/codecs/rt5663.c +++ b/sound/soc/codecs/rt5663.c @@ -72,6 +72,8 @@ struct rt5663_priv { static const struct reg_sequence rt5663_patch_list[] = { { 0x002a, 0x8020 }, { 0x0086, 0x0028 }, + { 0x0117, 0x0f28 }, + { 0x02fb, 0x8089 }, }; static const struct reg_default rt5663_v2_reg[] = { @@ -593,7 +595,7 @@ static const struct reg_default rt5663_reg[] = { { 0x0113, 0x2000 }, { 0x0114, 0x0000 }, { 0x0116, 0x0000 }, - { 0x0117, 0x0f00 }, + { 0x0117, 0x0f28 }, { 0x0118, 0x0006 }, { 0x0125, 0x2424 }, { 0x0126, 0x5550 }, @@ -693,7 +695,7 @@ static const struct reg_default rt5663_reg[] = { { 0x0251, 0x0000 }, { 0x0252, 0x028a }, { 0x02fa, 0x0000 }, - { 0x02fb, 0x00a4 }, + { 0x02fb, 0x8089 }, { 0x02fc, 0x0300 }, { 0x0300, 0x0000 }, { 0x03d0, 0x0000 }, @@ -1556,6 +1558,14 @@ static int rt5663_jack_detect(struct snd_soc_component *component, int jack_inse RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK, RT5663_PWR_MB | RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X); + snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, + RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | + RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, + RT5663_PWR_VREF1 | RT5663_PWR_VREF2); + msleep(20); + snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, + RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, + RT5663_PWR_FV1 | RT5663_PWR_FV2); snd_soc_component_update_bits(component, RT5663_AUTO_1MRC_CLK, RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN); snd_soc_component_update_bits(component, RT5663_IRQ_1, @@ -1613,7 +1623,10 @@ static int rt5663_jack_detect(struct snd_soc_component *component, int jack_inse break; default: rt5663->jack_type = SND_JACK_HEADPHONE; - + snd_soc_component_update_bits(component, + RT5663_PWR_ANLG_1, + RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK | + RT5663_PWR_VREF2_MASK, 0); if (rt5663->pdata.impedance_sensing_num) break; @@ -1638,6 +1651,9 @@ static int rt5663_jack_detect(struct snd_soc_component *component, int jack_inse if (rt5663->jack_type == SND_JACK_HEADSET) rt5663_enable_push_button_irq(component, false); rt5663->jack_type = 0; + snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, + RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK | + RT5663_PWR_VREF2_MASK, 0); } dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type); @@ -1840,8 +1856,8 @@ static irqreturn_t rt5663_irq(int irq, void *data) return IRQ_HANDLED; } -int rt5663_set_jack_detect(struct snd_soc_component *component, - struct snd_soc_jack *hs_jack) +static int rt5663_set_jack_detect(struct snd_soc_component *component, + struct snd_soc_jack *hs_jack, void *data) { struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); @@ -1851,7 +1867,6 @@ int rt5663_set_jack_detect(struct snd_soc_component *component, return 0; } -EXPORT_SYMBOL_GPL(rt5663_set_jack_detect); static bool rt5663_check_jd_status(struct snd_soc_component *component) { @@ -2307,6 +2322,8 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w, RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_SILENCE); } else { + snd_soc_component_update_bits(component, + RT5663_DACREF_LDO, 0x3e0e, 0x3a0a); snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003); snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS); @@ -2332,6 +2349,8 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x0); snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN); + snd_soc_component_update_bits(component, + RT5663_DACREF_LDO, 0x3e0e, 0); } break; @@ -3086,9 +3105,17 @@ static int rt5663_set_bias_level(struct snd_soc_component *component, break; case SND_SOC_BIAS_OFF: - snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, - RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | - RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0); + if (rt5663->jack_type != SND_JACK_HEADSET) + snd_soc_component_update_bits(component, + RT5663_PWR_ANLG_1, + RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | + RT5663_PWR_FV1 | RT5663_PWR_FV2 | + RT5663_PWR_MB_MASK, 0); + else + snd_soc_component_update_bits(component, + RT5663_PWR_ANLG_1, + RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, + RT5663_PWR_FV1 | RT5663_PWR_FV2); break; default: @@ -3216,10 +3243,10 @@ static const struct snd_soc_component_driver soc_component_dev_rt5663 = { .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets), .dapm_routes = rt5663_dapm_routes, .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes), + .set_jack = rt5663_set_jack_detect, .use_pmdown_time = 1, .endianness = 1, .non_legacy_dai_naming = 1, - }; static const struct regmap_config rt5663_v2_regmap = { @@ -3310,6 +3337,7 @@ static void rt5663_calibrate(struct rt5663_priv *rt5663) regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c); regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324); regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001); + regmap_write(rt5663->regmap, RT5663_VREFADJ_OP, 0x0f28); regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b); msleep(30); regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b); @@ -3344,6 +3372,7 @@ static void rt5663_calibrate(struct rt5663_priv *rt5663) regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003); regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c); regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32); + regmap_write(rt5663->regmap, RT5663_DUMMY_2, 0x8089); regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b); msleep(40); regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000); @@ -3578,15 +3607,9 @@ static int rt5663_i2c_probe(struct i2c_client *i2c, regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN); regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032); - regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be); - msleep(20); - regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be); regmap_update_bits(rt5663->regmap, RT5663_GPIO_2, RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK, RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN); - /* DACREF LDO control */ - regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e, - 0x3a0a); regmap_update_bits(rt5663->regmap, RT5663_RECMIX, RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON); regmap_update_bits(rt5663->regmap, RT5663_TDM_2, diff --git a/sound/soc/codecs/rt5663.h b/sound/soc/codecs/rt5663.h index 865203cc2034..794cf3fadf31 100644 --- a/sound/soc/codecs/rt5663.h +++ b/sound/soc/codecs/rt5663.h @@ -1125,8 +1125,6 @@ enum { RT5663_AD_STEREO_FILTER = 0x2, }; -int rt5663_set_jack_detect(struct snd_soc_component *component, - struct snd_soc_jack *hs_jack); int rt5663_sel_asrc_clk_src(struct snd_soc_component *component, unsigned int filter_mask, unsigned int clk_src); diff --git a/sound/soc/codecs/rt5668.c b/sound/soc/codecs/rt5668.c new file mode 100644 index 000000000000..3c19d03f2446 --- /dev/null +++ b/sound/soc/codecs/rt5668.c @@ -0,0 +1,2639 @@ +/* + * rt5668.c -- RT5668B ALSA SoC audio component driver + * + * Copyright 2018 Realtek Semiconductor Corp. + * Author: Bard Liao <bardliao@realtek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/platform_device.h> +#include <linux/spi/spi.h> +#include <linux/acpi.h> +#include <linux/gpio.h> +#include <linux/of_gpio.h> +#include <linux/regulator/consumer.h> +#include <linux/mutex.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/jack.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <sound/rt5668.h> + +#include "rl6231.h" +#include "rt5668.h" + +#define RT5668_NUM_SUPPLIES 3 + +static const char *rt5668_supply_names[RT5668_NUM_SUPPLIES] = { + "AVDD", + "MICVDD", + "VBAT", +}; + +struct rt5668_priv { + struct snd_soc_component *component; + struct rt5668_platform_data pdata; + struct regmap *regmap; + struct snd_soc_jack *hs_jack; + struct regulator_bulk_data supplies[RT5668_NUM_SUPPLIES]; + struct delayed_work jack_detect_work; + struct delayed_work jd_check_work; + struct mutex calibrate_mutex; + + int sysclk; + int sysclk_src; + int lrck[RT5668_AIFS]; + int bclk[RT5668_AIFS]; + int master[RT5668_AIFS]; + + int pll_src; + int pll_in; + int pll_out; + + int jack_type; +}; + +static const struct reg_default rt5668_reg[] = { + {0x0002, 0x8080}, + {0x0003, 0x8000}, + {0x0005, 0x0000}, + {0x0006, 0x0000}, + {0x0008, 0x800f}, + {0x000b, 0x0000}, + {0x0010, 0x4040}, + {0x0011, 0x0000}, + {0x0012, 0x1404}, + {0x0013, 0x1000}, + {0x0014, 0xa00a}, + {0x0015, 0x0404}, + {0x0016, 0x0404}, + {0x0019, 0xafaf}, + {0x001c, 0x2f2f}, + {0x001f, 0x0000}, + {0x0022, 0x5757}, + {0x0023, 0x0039}, + {0x0024, 0x000b}, + {0x0026, 0xc0c4}, + {0x0029, 0x8080}, + {0x002a, 0xa0a0}, + {0x002b, 0x0300}, + {0x0030, 0x0000}, + {0x003c, 0x0080}, + {0x0044, 0x0c0c}, + {0x0049, 0x0000}, + {0x0061, 0x0000}, + {0x0062, 0x0000}, + {0x0063, 0x003f}, + {0x0064, 0x0000}, + {0x0065, 0x0000}, + {0x0066, 0x0030}, + {0x0067, 0x0000}, + {0x006b, 0x0000}, + {0x006c, 0x0000}, + {0x006d, 0x2200}, + {0x006e, 0x0a10}, + {0x0070, 0x8000}, + {0x0071, 0x8000}, + {0x0073, 0x0000}, + {0x0074, 0x0000}, + {0x0075, 0x0002}, + {0x0076, 0x0001}, + {0x0079, 0x0000}, + {0x007a, 0x0000}, + {0x007b, 0x0000}, + {0x007c, 0x0100}, + {0x007e, 0x0000}, + {0x0080, 0x0000}, + {0x0081, 0x0000}, + {0x0082, 0x0000}, + {0x0083, 0x0000}, + {0x0084, 0x0000}, + {0x0085, 0x0000}, + {0x0086, 0x0005}, + {0x0087, 0x0000}, + {0x0088, 0x0000}, + {0x008c, 0x0003}, + {0x008d, 0x0000}, + {0x008e, 0x0060}, + {0x008f, 0x1000}, + {0x0091, 0x0c26}, + {0x0092, 0x0073}, + {0x0093, 0x0000}, + {0x0094, 0x0080}, + {0x0098, 0x0000}, + {0x009a, 0x0000}, + {0x009b, 0x0000}, + {0x009c, 0x0000}, + {0x009d, 0x0000}, + {0x009e, 0x100c}, + {0x009f, 0x0000}, + {0x00a0, 0x0000}, + {0x00a3, 0x0002}, + {0x00a4, 0x0001}, + {0x00ae, 0x2040}, + {0x00af, 0x0000}, + {0x00b6, 0x0000}, + {0x00b7, 0x0000}, + {0x00b8, 0x0000}, + {0x00b9, 0x0002}, + {0x00be, 0x0000}, + {0x00c0, 0x0160}, + {0x00c1, 0x82a0}, + {0x00c2, 0x0000}, + {0x00d0, 0x0000}, + {0x00d1, 0x2244}, + {0x00d2, 0x3300}, + {0x00d3, 0x2200}, + {0x00d4, 0x0000}, + {0x00d9, 0x0009}, + {0x00da, 0x0000}, + {0x00db, 0x0000}, + {0x00dc, 0x00c0}, + {0x00dd, 0x2220}, + {0x00de, 0x3131}, + {0x00df, 0x3131}, + {0x00e0, 0x3131}, + {0x00e2, 0x0000}, + {0x00e3, 0x4000}, + {0x00e4, 0x0aa0}, + {0x00e5, 0x3131}, + {0x00e6, 0x3131}, + {0x00e7, 0x3131}, + {0x00e8, 0x3131}, + {0x00ea, 0xb320}, + {0x00eb, 0x0000}, + {0x00f0, 0x0000}, + {0x00f1, 0x00d0}, + {0x00f2, 0x00d0}, + {0x00f6, 0x0000}, + {0x00fa, 0x0000}, + {0x00fb, 0x0000}, + {0x00fc, 0x0000}, + {0x00fd, 0x0000}, + {0x00fe, 0x10ec}, + {0x00ff, 0x6530}, + {0x0100, 0xa0a0}, + {0x010b, 0x0000}, + {0x010c, 0xae00}, + {0x010d, 0xaaa0}, + {0x010e, 0x8aa2}, + {0x010f, 0x02a2}, + {0x0110, 0xc000}, + {0x0111, 0x04a2}, + {0x0112, 0x2800}, + {0x0113, 0x0000}, + {0x0117, 0x0100}, + {0x0125, 0x0410}, + {0x0132, 0x6026}, + {0x0136, 0x5555}, + {0x0138, 0x3700}, + {0x013a, 0x2000}, + {0x013b, 0x2000}, + {0x013c, 0x2005}, + {0x013f, 0x0000}, + {0x0142, 0x0000}, + {0x0145, 0x0002}, + {0x0146, 0x0000}, + {0x0147, 0x0000}, + {0x0148, 0x0000}, + {0x0149, 0x0000}, + {0x0150, 0x79a1}, + {0x0151, 0x0000}, + {0x0160, 0x4ec0}, + {0x0161, 0x0080}, + {0x0162, 0x0200}, + {0x0163, 0x0800}, + {0x0164, 0x0000}, + {0x0165, 0x0000}, + {0x0166, 0x0000}, + {0x0167, 0x000f}, + {0x0168, 0x000f}, + {0x0169, 0x0021}, + {0x0190, 0x413d}, + {0x0194, 0x0000}, + {0x0195, 0x0000}, + {0x0197, 0x0022}, + {0x0198, 0x0000}, + {0x0199, 0x0000}, + {0x01af, 0x0000}, + {0x01b0, 0x0400}, + {0x01b1, 0x0000}, + {0x01b2, 0x0000}, + {0x01b3, 0x0000}, + {0x01b4, 0x0000}, + {0x01b5, 0x0000}, + {0x01b6, 0x01c3}, + {0x01b7, 0x02a0}, + {0x01b8, 0x03e9}, + {0x01b9, 0x1389}, + {0x01ba, 0xc351}, + {0x01bb, 0x0009}, + {0x01bc, 0x0018}, + {0x01bd, 0x002a}, + {0x01be, 0x004c}, + {0x01bf, 0x0097}, + {0x01c0, 0x433d}, + {0x01c1, 0x2800}, + {0x01c2, 0x0000}, + {0x01c3, 0x0000}, + {0x01c4, 0x0000}, + {0x01c5, 0x0000}, + {0x01c6, 0x0000}, + {0x01c7, 0x0000}, + {0x01c8, 0x40af}, + {0x01c9, 0x0702}, + {0x01ca, 0x0000}, + {0x01cb, 0x0000}, + {0x01cc, 0x5757}, + {0x01cd, 0x5757}, + {0x01ce, 0x5757}, + {0x01cf, 0x5757}, + {0x01d0, 0x5757}, + {0x01d1, 0x5757}, + {0x01d2, 0x5757}, + {0x01d3, 0x5757}, + {0x01d4, 0x5757}, + {0x01d5, 0x5757}, + {0x01d6, 0x0000}, + {0x01d7, 0x0008}, + {0x01d8, 0x0029}, + {0x01d9, 0x3333}, + {0x01da, 0x0000}, + {0x01db, 0x0004}, + {0x01dc, 0x0000}, + {0x01de, 0x7c00}, + {0x01df, 0x0320}, + {0x01e0, 0x06a1}, + {0x01e1, 0x0000}, + {0x01e2, 0x0000}, + {0x01e3, 0x0000}, + {0x01e4, 0x0000}, + {0x01e6, 0x0001}, + {0x01e7, 0x0000}, + {0x01e8, 0x0000}, + {0x01ea, 0x0000}, + {0x01eb, 0x0000}, + {0x01ec, 0x0000}, + {0x01ed, 0x0000}, + {0x01ee, 0x0000}, + {0x01ef, 0x0000}, + {0x01f0, 0x0000}, + {0x01f1, 0x0000}, + {0x01f2, 0x0000}, + {0x01f3, 0x0000}, + {0x01f4, 0x0000}, + {0x0210, 0x6297}, + {0x0211, 0xa005}, + {0x0212, 0x824c}, + {0x0213, 0xf7ff}, + {0x0214, 0xf24c}, + {0x0215, 0x0102}, + {0x0216, 0x00a3}, + {0x0217, 0x0048}, + {0x0218, 0xa2c0}, + {0x0219, 0x0400}, + {0x021a, 0x00c8}, + {0x021b, 0x00c0}, + {0x021c, 0x0000}, + {0x0250, 0x4500}, + {0x0251, 0x40b3}, + {0x0252, 0x0000}, + {0x0253, 0x0000}, + {0x0254, 0x0000}, + {0x0255, 0x0000}, + {0x0256, 0x0000}, + {0x0257, 0x0000}, + {0x0258, 0x0000}, + {0x0259, 0x0000}, + {0x025a, 0x0005}, + {0x0270, 0x0000}, + {0x02ff, 0x0110}, + {0x0300, 0x001f}, + {0x0301, 0x032c}, + {0x0302, 0x5f21}, + {0x0303, 0x4000}, + {0x0304, 0x4000}, + {0x0305, 0x06d5}, + {0x0306, 0x8000}, + {0x0307, 0x0700}, + {0x0310, 0x4560}, + {0x0311, 0xa4a8}, + {0x0312, 0x7418}, + {0x0313, 0x0000}, + {0x0314, 0x0006}, + {0x0315, 0xffff}, + {0x0316, 0xc400}, + {0x0317, 0x0000}, + {0x03c0, 0x7e00}, + {0x03c1, 0x8000}, + {0x03c2, 0x8000}, + {0x03c3, 0x8000}, + {0x03c4, 0x8000}, + {0x03c5, 0x8000}, + {0x03c6, 0x8000}, + {0x03c7, 0x8000}, + {0x03c8, 0x8000}, + {0x03c9, 0x8000}, + {0x03ca, 0x8000}, + {0x03cb, 0x8000}, + {0x03cc, 0x8000}, + {0x03d0, 0x0000}, + {0x03d1, 0x0000}, + {0x03d2, 0x0000}, + {0x03d3, 0x0000}, + {0x03d4, 0x2000}, + {0x03d5, 0x2000}, + {0x03d6, 0x0000}, + {0x03d7, 0x0000}, + {0x03d8, 0x2000}, + {0x03d9, 0x2000}, + {0x03da, 0x2000}, + {0x03db, 0x2000}, + {0x03dc, 0x0000}, + {0x03dd, 0x0000}, + {0x03de, 0x0000}, + {0x03df, 0x2000}, + {0x03e0, 0x0000}, + {0x03e1, 0x0000}, + {0x03e2, 0x0000}, + {0x03e3, 0x0000}, + {0x03e4, 0x0000}, + {0x03e5, 0x0000}, + {0x03e6, 0x0000}, + {0x03e7, 0x0000}, + {0x03e8, 0x0000}, + {0x03e9, 0x0000}, + {0x03ea, 0x0000}, + {0x03eb, 0x0000}, + {0x03ec, 0x0000}, + {0x03ed, 0x0000}, + {0x03ee, 0x0000}, + {0x03ef, 0x0000}, + {0x03f0, 0x0800}, + {0x03f1, 0x0800}, + {0x03f2, 0x0800}, + {0x03f3, 0x0800}, +}; + +static bool rt5668_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RT5668_RESET: + case RT5668_CBJ_CTRL_2: + case RT5668_INT_ST_1: + case RT5668_4BTN_IL_CMD_1: + case RT5668_AJD1_CTRL: + case RT5668_HP_CALIB_CTRL_1: + case RT5668_DEVICE_ID: + case RT5668_I2C_MODE: + case RT5668_HP_CALIB_CTRL_10: + case RT5668_EFUSE_CTRL_2: + case RT5668_JD_TOP_VC_VTRL: + case RT5668_HP_IMP_SENS_CTRL_19: + case RT5668_IL_CMD_1: + case RT5668_SAR_IL_CMD_2: + case RT5668_SAR_IL_CMD_4: + case RT5668_SAR_IL_CMD_10: + case RT5668_SAR_IL_CMD_11: + case RT5668_EFUSE_CTRL_6...RT5668_EFUSE_CTRL_11: + case RT5668_HP_CALIB_STA_1...RT5668_HP_CALIB_STA_11: + return true; + default: + return false; + } +} + +static bool rt5668_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RT5668_RESET: + case RT5668_VERSION_ID: + case RT5668_VENDOR_ID: + case RT5668_DEVICE_ID: + case RT5668_HP_CTRL_1: + case RT5668_HP_CTRL_2: + case RT5668_HPL_GAIN: + case RT5668_HPR_GAIN: + case RT5668_I2C_CTRL: + case RT5668_CBJ_BST_CTRL: + case RT5668_CBJ_CTRL_1: + case RT5668_CBJ_CTRL_2: + case RT5668_CBJ_CTRL_3: + case RT5668_CBJ_CTRL_4: + case RT5668_CBJ_CTRL_5: + case RT5668_CBJ_CTRL_6: + case RT5668_CBJ_CTRL_7: + case RT5668_DAC1_DIG_VOL: + case RT5668_STO1_ADC_DIG_VOL: + case RT5668_STO1_ADC_BOOST: + case RT5668_HP_IMP_GAIN_1: + case RT5668_HP_IMP_GAIN_2: + case RT5668_SIDETONE_CTRL: + case RT5668_STO1_ADC_MIXER: + case RT5668_AD_DA_MIXER: + case RT5668_STO1_DAC_MIXER: + case RT5668_A_DAC1_MUX: + case RT5668_DIG_INF2_DATA: + case RT5668_REC_MIXER: + case RT5668_CAL_REC: + case RT5668_ALC_BACK_GAIN: + case RT5668_PWR_DIG_1: + case RT5668_PWR_DIG_2: + case RT5668_PWR_ANLG_1: + case RT5668_PWR_ANLG_2: + case RT5668_PWR_ANLG_3: + case RT5668_PWR_MIXER: + case RT5668_PWR_VOL: + case RT5668_CLK_DET: + case RT5668_RESET_LPF_CTRL: + case RT5668_RESET_HPF_CTRL: + case RT5668_DMIC_CTRL_1: + case RT5668_I2S1_SDP: + case RT5668_I2S2_SDP: + case RT5668_ADDA_CLK_1: + case RT5668_ADDA_CLK_2: + case RT5668_I2S1_F_DIV_CTRL_1: + case RT5668_I2S1_F_DIV_CTRL_2: + case RT5668_TDM_CTRL: + case RT5668_TDM_ADDA_CTRL_1: + case RT5668_TDM_ADDA_CTRL_2: + case RT5668_DATA_SEL_CTRL_1: + case RT5668_TDM_TCON_CTRL: + case RT5668_GLB_CLK: + case RT5668_PLL_CTRL_1: + case RT5668_PLL_CTRL_2: + case RT5668_PLL_TRACK_1: + case RT5668_PLL_TRACK_2: + case RT5668_PLL_TRACK_3: + case RT5668_PLL_TRACK_4: + case RT5668_PLL_TRACK_5: + case RT5668_PLL_TRACK_6: + case RT5668_PLL_TRACK_11: + case RT5668_SDW_REF_CLK: + case RT5668_DEPOP_1: + case RT5668_DEPOP_2: + case RT5668_HP_CHARGE_PUMP_1: + case RT5668_HP_CHARGE_PUMP_2: + case RT5668_MICBIAS_1: + case RT5668_MICBIAS_2: + case RT5668_PLL_TRACK_12: + case RT5668_PLL_TRACK_14: + case RT5668_PLL2_CTRL_1: + case RT5668_PLL2_CTRL_2: + case RT5668_PLL2_CTRL_3: + case RT5668_PLL2_CTRL_4: + case RT5668_RC_CLK_CTRL: + case RT5668_I2S_M_CLK_CTRL_1: + case RT5668_I2S2_F_DIV_CTRL_1: + case RT5668_I2S2_F_DIV_CTRL_2: + case RT5668_EQ_CTRL_1: + case RT5668_EQ_CTRL_2: + case RT5668_IRQ_CTRL_1: + case RT5668_IRQ_CTRL_2: + case RT5668_IRQ_CTRL_3: + case RT5668_IRQ_CTRL_4: + case RT5668_INT_ST_1: + case RT5668_GPIO_CTRL_1: + case RT5668_GPIO_CTRL_2: + case RT5668_GPIO_CTRL_3: + case RT5668_HP_AMP_DET_CTRL_1: + case RT5668_HP_AMP_DET_CTRL_2: + case RT5668_MID_HP_AMP_DET: + case RT5668_LOW_HP_AMP_DET: + case RT5668_DELAY_BUF_CTRL: + case RT5668_SV_ZCD_1: + case RT5668_SV_ZCD_2: + case RT5668_IL_CMD_1: + case RT5668_IL_CMD_2: + case RT5668_IL_CMD_3: + case RT5668_IL_CMD_4: + case RT5668_IL_CMD_5: + case RT5668_IL_CMD_6: + case RT5668_4BTN_IL_CMD_1: + case RT5668_4BTN_IL_CMD_2: + case RT5668_4BTN_IL_CMD_3: + case RT5668_4BTN_IL_CMD_4: + case RT5668_4BTN_IL_CMD_5: + case RT5668_4BTN_IL_CMD_6: + case RT5668_4BTN_IL_CMD_7: + case RT5668_ADC_STO1_HP_CTRL_1: + case RT5668_ADC_STO1_HP_CTRL_2: + case RT5668_AJD1_CTRL: + case RT5668_JD1_THD: + case RT5668_JD2_THD: + case RT5668_JD_CTRL_1: + case RT5668_DUMMY_1: + case RT5668_DUMMY_2: + case RT5668_DUMMY_3: + case RT5668_DAC_ADC_DIG_VOL1: + case RT5668_BIAS_CUR_CTRL_2: + case RT5668_BIAS_CUR_CTRL_3: + case RT5668_BIAS_CUR_CTRL_4: + case RT5668_BIAS_CUR_CTRL_5: + case RT5668_BIAS_CUR_CTRL_6: + case RT5668_BIAS_CUR_CTRL_7: + case RT5668_BIAS_CUR_CTRL_8: + case RT5668_BIAS_CUR_CTRL_9: + case RT5668_BIAS_CUR_CTRL_10: + case RT5668_VREF_REC_OP_FB_CAP_CTRL: + case RT5668_CHARGE_PUMP_1: + case RT5668_DIG_IN_CTRL_1: + case RT5668_PAD_DRIVING_CTRL: + case RT5668_SOFT_RAMP_DEPOP: + case RT5668_CHOP_DAC: + case RT5668_CHOP_ADC: + case RT5668_CALIB_ADC_CTRL: + case RT5668_VOL_TEST: + case RT5668_SPKVDD_DET_STA: + case RT5668_TEST_MODE_CTRL_1: + case RT5668_TEST_MODE_CTRL_2: + case RT5668_TEST_MODE_CTRL_3: + case RT5668_TEST_MODE_CTRL_4: + case RT5668_TEST_MODE_CTRL_5: + case RT5668_PLL1_INTERNAL: + case RT5668_PLL2_INTERNAL: + case RT5668_STO_NG2_CTRL_1: + case RT5668_STO_NG2_CTRL_2: + case RT5668_STO_NG2_CTRL_3: + case RT5668_STO_NG2_CTRL_4: + case RT5668_STO_NG2_CTRL_5: + case RT5668_STO_NG2_CTRL_6: + case RT5668_STO_NG2_CTRL_7: + case RT5668_STO_NG2_CTRL_8: + case RT5668_STO_NG2_CTRL_9: + case RT5668_STO_NG2_CTRL_10: + case RT5668_STO1_DAC_SIL_DET: + case RT5668_SIL_PSV_CTRL1: + case RT5668_SIL_PSV_CTRL2: + case RT5668_SIL_PSV_CTRL3: + case RT5668_SIL_PSV_CTRL4: + case RT5668_SIL_PSV_CTRL5: + case RT5668_HP_IMP_SENS_CTRL_01: + case RT5668_HP_IMP_SENS_CTRL_02: + case RT5668_HP_IMP_SENS_CTRL_03: + case RT5668_HP_IMP_SENS_CTRL_04: + case RT5668_HP_IMP_SENS_CTRL_05: + case RT5668_HP_IMP_SENS_CTRL_06: + case RT5668_HP_IMP_SENS_CTRL_07: + case RT5668_HP_IMP_SENS_CTRL_08: + case RT5668_HP_IMP_SENS_CTRL_09: + case RT5668_HP_IMP_SENS_CTRL_10: + case RT5668_HP_IMP_SENS_CTRL_11: + case RT5668_HP_IMP_SENS_CTRL_12: + case RT5668_HP_IMP_SENS_CTRL_13: + case RT5668_HP_IMP_SENS_CTRL_14: + case RT5668_HP_IMP_SENS_CTRL_15: + case RT5668_HP_IMP_SENS_CTRL_16: + case RT5668_HP_IMP_SENS_CTRL_17: + case RT5668_HP_IMP_SENS_CTRL_18: + case RT5668_HP_IMP_SENS_CTRL_19: + case RT5668_HP_IMP_SENS_CTRL_20: + case RT5668_HP_IMP_SENS_CTRL_21: + case RT5668_HP_IMP_SENS_CTRL_22: + case RT5668_HP_IMP_SENS_CTRL_23: + case RT5668_HP_IMP_SENS_CTRL_24: + case RT5668_HP_IMP_SENS_CTRL_25: + case RT5668_HP_IMP_SENS_CTRL_26: + case RT5668_HP_IMP_SENS_CTRL_27: + case RT5668_HP_IMP_SENS_CTRL_28: + case RT5668_HP_IMP_SENS_CTRL_29: + case RT5668_HP_IMP_SENS_CTRL_30: + case RT5668_HP_IMP_SENS_CTRL_31: + case RT5668_HP_IMP_SENS_CTRL_32: + case RT5668_HP_IMP_SENS_CTRL_33: + case RT5668_HP_IMP_SENS_CTRL_34: + case RT5668_HP_IMP_SENS_CTRL_35: + case RT5668_HP_IMP_SENS_CTRL_36: + case RT5668_HP_IMP_SENS_CTRL_37: + case RT5668_HP_IMP_SENS_CTRL_38: + case RT5668_HP_IMP_SENS_CTRL_39: + case RT5668_HP_IMP_SENS_CTRL_40: + case RT5668_HP_IMP_SENS_CTRL_41: + case RT5668_HP_IMP_SENS_CTRL_42: + case RT5668_HP_IMP_SENS_CTRL_43: + case RT5668_HP_LOGIC_CTRL_1: + case RT5668_HP_LOGIC_CTRL_2: + case RT5668_HP_LOGIC_CTRL_3: + case RT5668_HP_CALIB_CTRL_1: + case RT5668_HP_CALIB_CTRL_2: + case RT5668_HP_CALIB_CTRL_3: + case RT5668_HP_CALIB_CTRL_4: + case RT5668_HP_CALIB_CTRL_5: + case RT5668_HP_CALIB_CTRL_6: + case RT5668_HP_CALIB_CTRL_7: + case RT5668_HP_CALIB_CTRL_9: + case RT5668_HP_CALIB_CTRL_10: + case RT5668_HP_CALIB_CTRL_11: + case RT5668_HP_CALIB_STA_1: + case RT5668_HP_CALIB_STA_2: + case RT5668_HP_CALIB_STA_3: + case RT5668_HP_CALIB_STA_4: + case RT5668_HP_CALIB_STA_5: + case RT5668_HP_CALIB_STA_6: + case RT5668_HP_CALIB_STA_7: + case RT5668_HP_CALIB_STA_8: + case RT5668_HP_CALIB_STA_9: + case RT5668_HP_CALIB_STA_10: + case RT5668_HP_CALIB_STA_11: + case RT5668_SAR_IL_CMD_1: + case RT5668_SAR_IL_CMD_2: + case RT5668_SAR_IL_CMD_3: + case RT5668_SAR_IL_CMD_4: + case RT5668_SAR_IL_CMD_5: + case RT5668_SAR_IL_CMD_6: + case RT5668_SAR_IL_CMD_7: + case RT5668_SAR_IL_CMD_8: + case RT5668_SAR_IL_CMD_9: + case RT5668_SAR_IL_CMD_10: + case RT5668_SAR_IL_CMD_11: + case RT5668_SAR_IL_CMD_12: + case RT5668_SAR_IL_CMD_13: + case RT5668_EFUSE_CTRL_1: + case RT5668_EFUSE_CTRL_2: + case RT5668_EFUSE_CTRL_3: + case RT5668_EFUSE_CTRL_4: + case RT5668_EFUSE_CTRL_5: + case RT5668_EFUSE_CTRL_6: + case RT5668_EFUSE_CTRL_7: + case RT5668_EFUSE_CTRL_8: + case RT5668_EFUSE_CTRL_9: + case RT5668_EFUSE_CTRL_10: + case RT5668_EFUSE_CTRL_11: + case RT5668_JD_TOP_VC_VTRL: + case RT5668_DRC1_CTRL_0: + case RT5668_DRC1_CTRL_1: + case RT5668_DRC1_CTRL_2: + case RT5668_DRC1_CTRL_3: + case RT5668_DRC1_CTRL_4: + case RT5668_DRC1_CTRL_5: + case RT5668_DRC1_CTRL_6: + case RT5668_DRC1_HARD_LMT_CTRL_1: + case RT5668_DRC1_HARD_LMT_CTRL_2: + case RT5668_DRC1_PRIV_1: + case RT5668_DRC1_PRIV_2: + case RT5668_DRC1_PRIV_3: + case RT5668_DRC1_PRIV_4: + case RT5668_DRC1_PRIV_5: + case RT5668_DRC1_PRIV_6: + case RT5668_DRC1_PRIV_7: + case RT5668_DRC1_PRIV_8: + case RT5668_EQ_AUTO_RCV_CTRL1: + case RT5668_EQ_AUTO_RCV_CTRL2: + case RT5668_EQ_AUTO_RCV_CTRL3: + case RT5668_EQ_AUTO_RCV_CTRL4: + case RT5668_EQ_AUTO_RCV_CTRL5: + case RT5668_EQ_AUTO_RCV_CTRL6: + case RT5668_EQ_AUTO_RCV_CTRL7: + case RT5668_EQ_AUTO_RCV_CTRL8: + case RT5668_EQ_AUTO_RCV_CTRL9: + case RT5668_EQ_AUTO_RCV_CTRL10: + case RT5668_EQ_AUTO_RCV_CTRL11: + case RT5668_EQ_AUTO_RCV_CTRL12: + case RT5668_EQ_AUTO_RCV_CTRL13: + case RT5668_ADC_L_EQ_LPF1_A1: + case RT5668_R_EQ_LPF1_A1: + case RT5668_L_EQ_LPF1_H0: + case RT5668_R_EQ_LPF1_H0: + case RT5668_L_EQ_BPF1_A1: + case RT5668_R_EQ_BPF1_A1: + case RT5668_L_EQ_BPF1_A2: + case RT5668_R_EQ_BPF1_A2: + case RT5668_L_EQ_BPF1_H0: + case RT5668_R_EQ_BPF1_H0: + case RT5668_L_EQ_BPF2_A1: + case RT5668_R_EQ_BPF2_A1: + case RT5668_L_EQ_BPF2_A2: + case RT5668_R_EQ_BPF2_A2: + case RT5668_L_EQ_BPF2_H0: + case RT5668_R_EQ_BPF2_H0: + case RT5668_L_EQ_BPF3_A1: + case RT5668_R_EQ_BPF3_A1: + case RT5668_L_EQ_BPF3_A2: + case RT5668_R_EQ_BPF3_A2: + case RT5668_L_EQ_BPF3_H0: + case RT5668_R_EQ_BPF3_H0: + case RT5668_L_EQ_BPF4_A1: + case RT5668_R_EQ_BPF4_A1: + case RT5668_L_EQ_BPF4_A2: + case RT5668_R_EQ_BPF4_A2: + case RT5668_L_EQ_BPF4_H0: + case RT5668_R_EQ_BPF4_H0: + case RT5668_L_EQ_HPF1_A1: + case RT5668_R_EQ_HPF1_A1: + case RT5668_L_EQ_HPF1_H0: + case RT5668_R_EQ_HPF1_H0: + case RT5668_L_EQ_PRE_VOL: + case RT5668_R_EQ_PRE_VOL: + case RT5668_L_EQ_POST_VOL: + case RT5668_R_EQ_POST_VOL: + case RT5668_I2C_MODE: + return true; + default: + return false; + } +} + +static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0); +static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); +static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); +static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); + +/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ +static const DECLARE_TLV_DB_RANGE(bst_tlv, + 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), + 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), + 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), + 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), + 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), + 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), + 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) +); + +/* Interface data select */ +static const char * const rt5668_data_select[] = { + "L/R", "R/L", "L/L", "R/R" +}; + +static SOC_ENUM_SINGLE_DECL(rt5668_if2_adc_enum, + RT5668_DIG_INF2_DATA, RT5668_IF2_ADC_SEL_SFT, rt5668_data_select); + +static SOC_ENUM_SINGLE_DECL(rt5668_if1_01_adc_enum, + RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC1_SEL_SFT, rt5668_data_select); + +static SOC_ENUM_SINGLE_DECL(rt5668_if1_23_adc_enum, + RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC2_SEL_SFT, rt5668_data_select); + +static SOC_ENUM_SINGLE_DECL(rt5668_if1_45_adc_enum, + RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC3_SEL_SFT, rt5668_data_select); + +static SOC_ENUM_SINGLE_DECL(rt5668_if1_67_adc_enum, + RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC4_SEL_SFT, rt5668_data_select); + +static const struct snd_kcontrol_new rt5668_if2_adc_swap_mux = + SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5668_if2_adc_enum); + +static const struct snd_kcontrol_new rt5668_if1_01_adc_swap_mux = + SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5668_if1_01_adc_enum); + +static const struct snd_kcontrol_new rt5668_if1_23_adc_swap_mux = + SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5668_if1_23_adc_enum); + +static const struct snd_kcontrol_new rt5668_if1_45_adc_swap_mux = + SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5668_if1_45_adc_enum); + +static const struct snd_kcontrol_new rt5668_if1_67_adc_swap_mux = + SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5668_if1_67_adc_enum); + +static void rt5668_reset(struct regmap *regmap) +{ + regmap_write(regmap, RT5668_RESET, 0); + regmap_write(regmap, RT5668_I2C_MODE, 1); +} +/** + * rt5668_sel_asrc_clk_src - select ASRC clock source for a set of filters + * @component: SoC audio component device. + * @filter_mask: mask of filters. + * @clk_src: clock source + * + * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5668 can + * only support standard 32fs or 64fs i2s format, ASRC should be enabled to + * support special i2s clock format such as Intel's 100fs(100 * sampling rate). + * ASRC function will track i2s clock and generate a corresponding system clock + * for codec. This function provides an API to select the clock source for a + * set of filters specified by the mask. And the component driver will turn on + * ASRC for these filters if ASRC is selected as their clock source. + */ +int rt5668_sel_asrc_clk_src(struct snd_soc_component *component, + unsigned int filter_mask, unsigned int clk_src) +{ + + switch (clk_src) { + case RT5668_CLK_SEL_SYS: + case RT5668_CLK_SEL_I2S1_ASRC: + case RT5668_CLK_SEL_I2S2_ASRC: + break; + + default: + return -EINVAL; + } + + if (filter_mask & RT5668_DA_STEREO1_FILTER) { + snd_soc_component_update_bits(component, RT5668_PLL_TRACK_2, + RT5668_FILTER_CLK_SEL_MASK, + clk_src << RT5668_FILTER_CLK_SEL_SFT); + } + + if (filter_mask & RT5668_AD_STEREO1_FILTER) { + snd_soc_component_update_bits(component, RT5668_PLL_TRACK_3, + RT5668_FILTER_CLK_SEL_MASK, + clk_src << RT5668_FILTER_CLK_SEL_SFT); + } + + return 0; +} +EXPORT_SYMBOL_GPL(rt5668_sel_asrc_clk_src); + +static int rt5668_button_detect(struct snd_soc_component *component) +{ + int btn_type, val; + + val = snd_soc_component_read32(component, RT5668_4BTN_IL_CMD_1); + btn_type = val & 0xfff0; + snd_soc_component_write(component, RT5668_4BTN_IL_CMD_1, val); + pr_debug("%s btn_type=%x\n", __func__, btn_type); + + return btn_type; +} + +static void rt5668_enable_push_button_irq(struct snd_soc_component *component, + bool enable) +{ + if (enable) { + snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, + RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_EN); + snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13, + RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_BTN); + snd_soc_component_write(component, RT5668_IL_CMD_1, 0x0040); + snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, + RT5668_4BTN_IL_MASK | RT5668_4BTN_IL_RST_MASK, + RT5668_4BTN_IL_EN | RT5668_4BTN_IL_NOR); + snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3, + RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_EN); + } else { + snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3, + RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_DIS); + snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, + RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_DIS); + snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, + RT5668_4BTN_IL_MASK, RT5668_4BTN_IL_DIS); + snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, + RT5668_4BTN_IL_RST_MASK, RT5668_4BTN_IL_RST); + snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13, + RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_TYPE); + } +} + +/** + * rt5668_headset_detect - Detect headset. + * @component: SoC audio component device. + * @jack_insert: Jack insert or not. + * + * Detect whether is headset or not when jack inserted. + * + * Returns detect status. + */ +static int rt5668_headset_detect(struct snd_soc_component *component, + int jack_insert) +{ + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(component); + unsigned int val, count; + + if (jack_insert) { + snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); + snd_soc_dapm_sync(dapm); + snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1, + RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_HIGH); + + count = 0; + val = snd_soc_component_read32(component, RT5668_CBJ_CTRL_2) + & RT5668_JACK_TYPE_MASK; + while (val == 0 && count < 50) { + usleep_range(10000, 15000); + val = snd_soc_component_read32(component, + RT5668_CBJ_CTRL_2) & RT5668_JACK_TYPE_MASK; + count++; + } + + switch (val) { + case 0x1: + case 0x2: + rt5668->jack_type = SND_JACK_HEADSET; + rt5668_enable_push_button_irq(component, true); + break; + default: + rt5668->jack_type = SND_JACK_HEADPHONE; + } + + } else { + rt5668_enable_push_button_irq(component, false); + snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1, + RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_LOW); + snd_soc_dapm_disable_pin(dapm, "CBJ Power"); + snd_soc_dapm_sync(dapm); + + rt5668->jack_type = 0; + } + + dev_dbg(component->dev, "jack_type = %d\n", rt5668->jack_type); + return rt5668->jack_type; +} + +static irqreturn_t rt5668_irq(int irq, void *data) +{ + struct rt5668_priv *rt5668 = data; + + mod_delayed_work(system_power_efficient_wq, + &rt5668->jack_detect_work, msecs_to_jiffies(250)); + + return IRQ_HANDLED; +} + +static void rt5668_jd_check_handler(struct work_struct *work) +{ + struct rt5668_priv *rt5668 = container_of(work, struct rt5668_priv, + jd_check_work.work); + + if (snd_soc_component_read32(rt5668->component, RT5668_AJD1_CTRL) + & RT5668_JDH_RS_MASK) { + /* jack out */ + rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0); + + snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type, + SND_JACK_HEADSET | + SND_JACK_BTN_0 | SND_JACK_BTN_1 | + SND_JACK_BTN_2 | SND_JACK_BTN_3); + } else { + schedule_delayed_work(&rt5668->jd_check_work, 500); + } +} + +static int rt5668_set_jack_detect(struct snd_soc_component *component, + struct snd_soc_jack *hs_jack, void *data) +{ + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + + switch (rt5668->pdata.jd_src) { + case RT5668_JD1: + snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_2, + RT5668_EXT_JD_SRC, RT5668_EXT_JD_SRC_MANUAL); + snd_soc_component_write(component, RT5668_CBJ_CTRL_1, 0xd002); + snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_3, + RT5668_CBJ_IN_BUF_EN, RT5668_CBJ_IN_BUF_EN); + snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, + RT5668_SAR_POW_MASK, RT5668_SAR_POW_EN); + regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, + RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_IRQ); + regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL, + RT5668_POW_IRQ | RT5668_POW_JDH | + RT5668_POW_ANA, RT5668_POW_IRQ | + RT5668_POW_JDH | RT5668_POW_ANA); + regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_2, + RT5668_PWR_JDH | RT5668_PWR_JDL, + RT5668_PWR_JDH | RT5668_PWR_JDL); + regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2, + RT5668_JD1_EN_MASK | RT5668_JD1_POL_MASK, + RT5668_JD1_EN | RT5668_JD1_POL_NOR); + mod_delayed_work(system_power_efficient_wq, + &rt5668->jack_detect_work, msecs_to_jiffies(250)); + break; + + case RT5668_JD_NULL: + regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2, + RT5668_JD1_EN_MASK, RT5668_JD1_DIS); + regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL, + RT5668_POW_JDH | RT5668_POW_JDL, 0); + break; + + default: + dev_warn(component->dev, "Wrong JD source\n"); + break; + } + + rt5668->hs_jack = hs_jack; + + return 0; +} + +static void rt5668_jack_detect_handler(struct work_struct *work) +{ + struct rt5668_priv *rt5668 = + container_of(work, struct rt5668_priv, jack_detect_work.work); + int val, btn_type; + + while (!rt5668->component) + usleep_range(10000, 15000); + + while (!rt5668->component->card->instantiated) + usleep_range(10000, 15000); + + mutex_lock(&rt5668->calibrate_mutex); + + val = snd_soc_component_read32(rt5668->component, RT5668_AJD1_CTRL) + & RT5668_JDH_RS_MASK; + if (!val) { + /* jack in */ + if (rt5668->jack_type == 0) { + /* jack was out, report jack type */ + rt5668->jack_type = + rt5668_headset_detect(rt5668->component, 1); + } else { + /* jack is already in, report button event */ + rt5668->jack_type = SND_JACK_HEADSET; + btn_type = rt5668_button_detect(rt5668->component); + /** + * rt5668 can report three kinds of button behavior, + * one click, double click and hold. However, + * currently we will report button pressed/released + * event. So all the three button behaviors are + * treated as button pressed. + */ + switch (btn_type) { + case 0x8000: + case 0x4000: + case 0x2000: + rt5668->jack_type |= SND_JACK_BTN_0; + break; + case 0x1000: + case 0x0800: + case 0x0400: + rt5668->jack_type |= SND_JACK_BTN_1; + break; + case 0x0200: + case 0x0100: + case 0x0080: + rt5668->jack_type |= SND_JACK_BTN_2; + break; + case 0x0040: + case 0x0020: + case 0x0010: + rt5668->jack_type |= SND_JACK_BTN_3; + break; + case 0x0000: /* unpressed */ + break; + default: + btn_type = 0; + dev_err(rt5668->component->dev, + "Unexpected button code 0x%04x\n", + btn_type); + break; + } + } + } else { + /* jack out */ + rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0); + } + + snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type, + SND_JACK_HEADSET | + SND_JACK_BTN_0 | SND_JACK_BTN_1 | + SND_JACK_BTN_2 | SND_JACK_BTN_3); + + if (rt5668->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | + SND_JACK_BTN_2 | SND_JACK_BTN_3)) + schedule_delayed_work(&rt5668->jd_check_work, 0); + else + cancel_delayed_work_sync(&rt5668->jd_check_work); + + mutex_unlock(&rt5668->calibrate_mutex); +} + +static const struct snd_kcontrol_new rt5668_snd_controls[] = { + /* Headphone Output Volume */ + SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5668_HPL_GAIN, + RT5668_HPR_GAIN, RT5668_G_HP_SFT, 15, 1, hp_vol_tlv), + + /* DAC Digital Volume */ + SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5668_DAC1_DIG_VOL, + RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 175, 0, dac_vol_tlv), + + /* IN Boost Volume */ + SOC_SINGLE_TLV("CBJ Boost Volume", RT5668_CBJ_BST_CTRL, + RT5668_BST_CBJ_SFT, 8, 0, bst_tlv), + + /* ADC Digital Volume Control */ + SOC_DOUBLE("STO1 ADC Capture Switch", RT5668_STO1_ADC_DIG_VOL, + RT5668_L_MUTE_SFT, RT5668_R_MUTE_SFT, 1, 1), + SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5668_STO1_ADC_DIG_VOL, + RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 127, 0, adc_vol_tlv), + + /* ADC Boost Volume Control */ + SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5668_STO1_ADC_BOOST, + RT5668_STO1_ADC_L_BST_SFT, RT5668_STO1_ADC_R_BST_SFT, + 3, 0, adc_bst_tlv), +}; + + +static int rt5668_div_sel(struct rt5668_priv *rt5668, + int target, const int div[], int size) +{ + int i; + + if (rt5668->sysclk < target) { + pr_err("sysclk rate %d is too low\n", + rt5668->sysclk); + return 0; + } + + for (i = 0; i < size - 1; i++) { + pr_info("div[%d]=%d\n", i, div[i]); + if (target * div[i] == rt5668->sysclk) + return i; + if (target * div[i + 1] > rt5668->sysclk) { + pr_err("can't find div for sysclk %d\n", + rt5668->sysclk); + return i; + } + } + + if (target * div[i] < rt5668->sysclk) + pr_err("sysclk rate %d is too high\n", + rt5668->sysclk); + + return size - 1; + +} + +/** + * set_dmic_clk - Set parameter of dmic. + * + * @w: DAPM widget. + * @kcontrol: The kcontrol of this widget. + * @event: Event id. + * + * Choose dmic clock between 1MHz and 3MHz. + * It is better for clock to approximate 3MHz. + */ +static int set_dmic_clk(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + int idx = -EINVAL; + static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; + + idx = rt5668_div_sel(rt5668, 1500000, div, ARRAY_SIZE(div)); + + snd_soc_component_update_bits(component, RT5668_DMIC_CTRL_1, + RT5668_DMIC_CLK_MASK, idx << RT5668_DMIC_CLK_SFT); + + return 0; +} + +static int set_filter_clk(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + int ref, val, reg, idx = -EINVAL; + static const int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; + + val = snd_soc_component_read32(component, RT5668_GPIO_CTRL_1) & + RT5668_GP4_PIN_MASK; + if (w->shift == RT5668_PWR_ADC_S1F_BIT && + val == RT5668_GP4_PIN_ADCDAT2) + ref = 256 * rt5668->lrck[RT5668_AIF2]; + else + ref = 256 * rt5668->lrck[RT5668_AIF1]; + + idx = rt5668_div_sel(rt5668, ref, div, ARRAY_SIZE(div)); + + if (w->shift == RT5668_PWR_ADC_S1F_BIT) + reg = RT5668_PLL_TRACK_3; + else + reg = RT5668_PLL_TRACK_2; + + snd_soc_component_update_bits(component, reg, + RT5668_FILTER_CLK_SEL_MASK, idx << RT5668_FILTER_CLK_SEL_SFT); + + return 0; +} + +static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, + struct snd_soc_dapm_widget *sink) +{ + unsigned int val; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + val = snd_soc_component_read32(component, RT5668_GLB_CLK); + val &= RT5668_SCLK_SRC_MASK; + if (val == RT5668_SCLK_SRC_PLL1) + return 1; + else + return 0; +} + +static int is_using_asrc(struct snd_soc_dapm_widget *w, + struct snd_soc_dapm_widget *sink) +{ + unsigned int reg, shift, val; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + switch (w->shift) { + case RT5668_ADC_STO1_ASRC_SFT: + reg = RT5668_PLL_TRACK_3; + shift = RT5668_FILTER_CLK_SEL_SFT; + break; + case RT5668_DAC_STO1_ASRC_SFT: + reg = RT5668_PLL_TRACK_2; + shift = RT5668_FILTER_CLK_SEL_SFT; + break; + default: + return 0; + } + + val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; + switch (val) { + case RT5668_CLK_SEL_I2S1_ASRC: + case RT5668_CLK_SEL_I2S2_ASRC: + return 1; + default: + return 0; + } + +} + +/* Digital Mixer */ +static const struct snd_kcontrol_new rt5668_sto1_adc_l_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER, + RT5668_M_STO1_ADC_L1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER, + RT5668_M_STO1_ADC_L2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER, + RT5668_M_STO1_ADC_R1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER, + RT5668_M_STO1_ADC_R2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5668_dac_l_mix[] = { + SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER, + RT5668_M_ADCMIX_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER, + RT5668_M_DAC1_L_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5668_dac_r_mix[] = { + SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER, + RT5668_M_ADCMIX_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER, + RT5668_M_DAC1_R_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5668_sto1_dac_l_mix[] = { + SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER, + RT5668_M_DAC_L1_STO_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER, + RT5668_M_DAC_R1_STO_L_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5668_sto1_dac_r_mix[] = { + SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER, + RT5668_M_DAC_L1_STO_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER, + RT5668_M_DAC_R1_STO_R_SFT, 1, 1), +}; + +/* Analog Input Mixer */ +static const struct snd_kcontrol_new rt5668_rec1_l_mix[] = { + SOC_DAPM_SINGLE("CBJ Switch", RT5668_REC_MIXER, + RT5668_M_CBJ_RM1_L_SFT, 1, 1), +}; + +/* STO1 ADC1 Source */ +/* MX-26 [13] [5] */ +static const char * const rt5668_sto1_adc1_src[] = { + "DAC MIX", "ADC" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5668_sto1_adc1l_enum, RT5668_STO1_ADC_MIXER, + RT5668_STO1_ADC1L_SRC_SFT, rt5668_sto1_adc1_src); + +static const struct snd_kcontrol_new rt5668_sto1_adc1l_mux = + SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1l_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5668_sto1_adc1r_enum, RT5668_STO1_ADC_MIXER, + RT5668_STO1_ADC1R_SRC_SFT, rt5668_sto1_adc1_src); + +static const struct snd_kcontrol_new rt5668_sto1_adc1r_mux = + SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1r_enum); + +/* STO1 ADC Source */ +/* MX-26 [11:10] [3:2] */ +static const char * const rt5668_sto1_adc_src[] = { + "ADC1 L", "ADC1 R" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5668_sto1_adcl_enum, RT5668_STO1_ADC_MIXER, + RT5668_STO1_ADCL_SRC_SFT, rt5668_sto1_adc_src); + +static const struct snd_kcontrol_new rt5668_sto1_adcl_mux = + SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5668_sto1_adcl_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5668_sto1_adcr_enum, RT5668_STO1_ADC_MIXER, + RT5668_STO1_ADCR_SRC_SFT, rt5668_sto1_adc_src); + +static const struct snd_kcontrol_new rt5668_sto1_adcr_mux = + SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5668_sto1_adcr_enum); + +/* STO1 ADC2 Source */ +/* MX-26 [12] [4] */ +static const char * const rt5668_sto1_adc2_src[] = { + "DAC MIX", "DMIC" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5668_sto1_adc2l_enum, RT5668_STO1_ADC_MIXER, + RT5668_STO1_ADC2L_SRC_SFT, rt5668_sto1_adc2_src); + +static const struct snd_kcontrol_new rt5668_sto1_adc2l_mux = + SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5668_sto1_adc2l_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5668_sto1_adc2r_enum, RT5668_STO1_ADC_MIXER, + RT5668_STO1_ADC2R_SRC_SFT, rt5668_sto1_adc2_src); + +static const struct snd_kcontrol_new rt5668_sto1_adc2r_mux = + SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5668_sto1_adc2r_enum); + +/* MX-79 [6:4] I2S1 ADC data location */ +static const unsigned int rt5668_if1_adc_slot_values[] = { + 0, + 2, + 4, + 6, +}; + +static const char * const rt5668_if1_adc_slot_src[] = { + "Slot 0", "Slot 2", "Slot 4", "Slot 6" +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_if1_adc_slot_enum, + RT5668_TDM_CTRL, RT5668_TDM_ADC_LCA_SFT, RT5668_TDM_ADC_LCA_MASK, + rt5668_if1_adc_slot_src, rt5668_if1_adc_slot_values); + +static const struct snd_kcontrol_new rt5668_if1_adc_slot_mux = + SOC_DAPM_ENUM("IF1 ADC Slot location", rt5668_if1_adc_slot_enum); + +/* Analog DAC L1 Source, Analog DAC R1 Source*/ +/* MX-2B [4], MX-2B [0]*/ +static const char * const rt5668_alg_dac1_src[] = { + "Stereo1 DAC Mixer", "DAC1" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5668_alg_dac_l1_enum, RT5668_A_DAC1_MUX, + RT5668_A_DACL1_SFT, rt5668_alg_dac1_src); + +static const struct snd_kcontrol_new rt5668_alg_dac_l1_mux = + SOC_DAPM_ENUM("Analog DAC L1 Source", rt5668_alg_dac_l1_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5668_alg_dac_r1_enum, RT5668_A_DAC1_MUX, + RT5668_A_DACR1_SFT, rt5668_alg_dac1_src); + +static const struct snd_kcontrol_new rt5668_alg_dac_r1_mux = + SOC_DAPM_ENUM("Analog DAC R1 Source", rt5668_alg_dac_r1_enum); + +/* Out Switch */ +static const struct snd_kcontrol_new hpol_switch = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1, + RT5668_L_MUTE_SFT, 1, 1); +static const struct snd_kcontrol_new hpor_switch = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1, + RT5668_R_MUTE_SFT, 1, 1); + +static int rt5668_hp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + snd_soc_component_write(component, + RT5668_HP_LOGIC_CTRL_2, 0x0012); + snd_soc_component_write(component, + RT5668_HP_CTRL_2, 0x6000); + snd_soc_component_update_bits(component, RT5668_STO_NG2_CTRL_1, + RT5668_NG2_EN_MASK, RT5668_NG2_EN); + snd_soc_component_update_bits(component, + RT5668_DEPOP_1, 0x60, 0x60); + break; + + case SND_SOC_DAPM_POST_PMD: + snd_soc_component_update_bits(component, + RT5668_DEPOP_1, 0x60, 0x0); + snd_soc_component_write(component, + RT5668_HP_CTRL_2, 0x0000); + break; + + default: + return 0; + } + + return 0; + +} + +static int set_dmic_power(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + switch (event) { + case SND_SOC_DAPM_POST_PMU: + /*Add delay to avoid pop noise*/ + msleep(150); + break; + + default: + return 0; + } + + return 0; +} + +static int rt5655_set_verf(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + switch (w->shift) { + case RT5668_PWR_VREF1_BIT: + snd_soc_component_update_bits(component, + RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 0); + break; + + case RT5668_PWR_VREF2_BIT: + snd_soc_component_update_bits(component, + RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 0); + break; + + default: + break; + } + break; + + case SND_SOC_DAPM_POST_PMU: + usleep_range(15000, 20000); + switch (w->shift) { + case RT5668_PWR_VREF1_BIT: + snd_soc_component_update_bits(component, + RT5668_PWR_ANLG_1, RT5668_PWR_FV1, + RT5668_PWR_FV1); + break; + + case RT5668_PWR_VREF2_BIT: + snd_soc_component_update_bits(component, + RT5668_PWR_ANLG_1, RT5668_PWR_FV2, + RT5668_PWR_FV2); + break; + + default: + break; + } + break; + + default: + return 0; + } + + return 0; +} + +static const unsigned int rt5668_adcdat_pin_values[] = { + 1, + 3, +}; + +static const char * const rt5668_adcdat_pin_select[] = { + "ADCDAT1", + "ADCDAT2", +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_adcdat_pin_enum, + RT5668_GPIO_CTRL_1, RT5668_GP4_PIN_SFT, RT5668_GP4_PIN_MASK, + rt5668_adcdat_pin_select, rt5668_adcdat_pin_values); + +static const struct snd_kcontrol_new rt5668_adcdat_pin_ctrl = + SOC_DAPM_ENUM("ADCDAT", rt5668_adcdat_pin_enum); + +static const struct snd_soc_dapm_widget rt5668_dapm_widgets[] = { + SND_SOC_DAPM_SUPPLY("LDO2", RT5668_PWR_ANLG_3, RT5668_PWR_LDO2_BIT, + 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PLL1", RT5668_PWR_ANLG_3, RT5668_PWR_PLL_BIT, + 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PLL2B", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2B_BIT, + 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PLL2F", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2F_BIT, + 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Vref1", RT5668_PWR_ANLG_1, RT5668_PWR_VREF1_BIT, 0, + rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_SUPPLY("Vref2", RT5668_PWR_ANLG_1, RT5668_PWR_VREF2_BIT, 0, + rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + + /* ASRC */ + SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5668_PLL_TRACK_1, + RT5668_DAC_STO1_ASRC_SFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5668_PLL_TRACK_1, + RT5668_ADC_STO1_ASRC_SFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5668_PLL_TRACK_1, + RT5668_AD_ASRC_SFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5668_PLL_TRACK_1, + RT5668_DA_ASRC_SFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5668_PLL_TRACK_1, + RT5668_DMIC_ASRC_SFT, 0, NULL, 0), + + /* Input Side */ + SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5668_PWR_ANLG_2, RT5668_PWR_MB1_BIT, + 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5668_PWR_ANLG_2, RT5668_PWR_MB2_BIT, + 0, NULL, 0), + + /* Input Lines */ + SND_SOC_DAPM_INPUT("DMIC L1"), + SND_SOC_DAPM_INPUT("DMIC R1"), + + SND_SOC_DAPM_INPUT("IN1P"), + + SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, + set_dmic_clk, SND_SOC_DAPM_PRE_PMU), + SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5668_DMIC_CTRL_1, + RT5668_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), + + /* Boost */ + SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, + 0, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("CBJ Power", RT5668_PWR_ANLG_3, + RT5668_PWR_CBJ_BIT, 0, NULL, 0), + + /* REC Mixer */ + SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_rec1_l_mix, + ARRAY_SIZE(rt5668_rec1_l_mix)), + SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5668_PWR_ANLG_2, + RT5668_PWR_RM1_L_BIT, 0, NULL, 0), + + /* ADCs */ + SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5668_PWR_DIG_1, + RT5668_PWR_ADC_L1_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5668_PWR_DIG_1, + RT5668_PWR_ADC_R1_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5668_CHOP_ADC, + RT5668_CKGEN_ADC1_SFT, 0, NULL, 0), + + /* ADC Mux */ + SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, + &rt5668_sto1_adc1l_mux), + SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, + &rt5668_sto1_adc1r_mux), + SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, + &rt5668_sto1_adc2l_mux), + SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, + &rt5668_sto1_adc2r_mux), + SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, + &rt5668_sto1_adcl_mux), + SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, + &rt5668_sto1_adcr_mux), + SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, + &rt5668_if1_adc_slot_mux), + + /* ADC Mixer */ + SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5668_PWR_DIG_2, + RT5668_PWR_ADC_S1F_BIT, 0, set_filter_clk, + SND_SOC_DAPM_PRE_PMU), + SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5668_STO1_ADC_DIG_VOL, + RT5668_L_MUTE_SFT, 1, rt5668_sto1_adc_l_mix, + ARRAY_SIZE(rt5668_sto1_adc_l_mix)), + SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5668_STO1_ADC_DIG_VOL, + RT5668_R_MUTE_SFT, 1, rt5668_sto1_adc_r_mix, + ARRAY_SIZE(rt5668_sto1_adc_r_mix)), + + /* ADC PGA */ + SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* Digital Interface */ + SND_SOC_DAPM_SUPPLY("I2S1", RT5668_PWR_DIG_1, RT5668_PWR_I2S1_BIT, + 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("I2S2", RT5668_PWR_DIG_1, RT5668_PWR_I2S2_BIT, + 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* Digital Interface Select */ + SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, + &rt5668_if1_01_adc_swap_mux), + SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, + &rt5668_if1_23_adc_swap_mux), + SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, + &rt5668_if1_45_adc_swap_mux), + SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, + &rt5668_if1_67_adc_swap_mux), + SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, + &rt5668_if2_adc_swap_mux), + + SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, + &rt5668_adcdat_pin_ctrl), + + /* Audio Interface */ + SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, + RT5668_I2S1_SDP, RT5668_SEL_ADCDAT_SFT, 1), + SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, + RT5668_I2S2_SDP, RT5668_I2S2_PIN_CFG_SFT, 1), + SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + + /* Output Side */ + /* DAC mixer before sound effect */ + SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, + rt5668_dac_l_mix, ARRAY_SIZE(rt5668_dac_l_mix)), + SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, + rt5668_dac_r_mix, ARRAY_SIZE(rt5668_dac_r_mix)), + + /* DAC channel Mux */ + SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, + &rt5668_alg_dac_l1_mux), + SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, + &rt5668_alg_dac_r1_mux), + + /* DAC Mixer */ + SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5668_PWR_DIG_2, + RT5668_PWR_DAC_S1F_BIT, 0, set_filter_clk, + SND_SOC_DAPM_PRE_PMU), + SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, + rt5668_sto1_dac_l_mix, ARRAY_SIZE(rt5668_sto1_dac_l_mix)), + SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, + rt5668_sto1_dac_r_mix, ARRAY_SIZE(rt5668_sto1_dac_r_mix)), + + /* DACs */ + SND_SOC_DAPM_DAC("DAC L1", NULL, RT5668_PWR_DIG_1, + RT5668_PWR_DAC_L1_BIT, 0), + SND_SOC_DAPM_DAC("DAC R1", NULL, RT5668_PWR_DIG_1, + RT5668_PWR_DAC_R1_BIT, 0), + SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5668_CHOP_DAC, + RT5668_CKGEN_DAC1_SFT, 0, NULL, 0), + + /* HPO */ + SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5668_hp_event, + SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), + + SND_SOC_DAPM_SUPPLY("HP Amp L", RT5668_PWR_ANLG_1, + RT5668_PWR_HA_L_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("HP Amp R", RT5668_PWR_ANLG_1, + RT5668_PWR_HA_R_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5668_DEPOP_1, + RT5668_PUMP_EN_SFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5668_DEPOP_1, + RT5668_CAPLESS_EN_SFT, 0, NULL, 0), + + SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, + &hpol_switch), + SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, + &hpor_switch), + + /* CLK DET */ + SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5668_CLK_DET, + RT5668_SYS_CLK_DET_SFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5668_CLK_DET, + RT5668_PLL1_CLK_DET_SFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5668_CLK_DET, + RT5668_PLL2_CLK_DET_SFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLKDET", RT5668_CLK_DET, + RT5668_POW_CLK_DET_SFT, 0, NULL, 0), + + /* Output Lines */ + SND_SOC_DAPM_OUTPUT("HPOL"), + SND_SOC_DAPM_OUTPUT("HPOR"), + +}; + +static const struct snd_soc_dapm_route rt5668_dapm_routes[] = { + /*PLL*/ + {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, + {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, + + /*ASRC*/ + {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, + {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, + {"ADC STO1 ASRC", NULL, "AD ASRC"}, + {"DAC STO1 ASRC", NULL, "DA ASRC"}, + + /*Vref*/ + {"MICBIAS1", NULL, "Vref1"}, + {"MICBIAS1", NULL, "Vref2"}, + {"MICBIAS2", NULL, "Vref1"}, + {"MICBIAS2", NULL, "Vref2"}, + + {"CLKDET SYS", NULL, "CLKDET"}, + + {"IN1P", NULL, "LDO2"}, + + {"BST1 CBJ", NULL, "IN1P"}, + {"BST1 CBJ", NULL, "CBJ Power"}, + {"CBJ Power", NULL, "Vref2"}, + + {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, + {"RECMIX1L", NULL, "RECMIX1L Power"}, + + {"ADC1 L", NULL, "RECMIX1L"}, + {"ADC1 L", NULL, "ADC1 L Power"}, + {"ADC1 L", NULL, "ADC1 clock"}, + + {"DMIC L1", NULL, "DMIC CLK"}, + {"DMIC L1", NULL, "DMIC1 Power"}, + {"DMIC R1", NULL, "DMIC CLK"}, + {"DMIC R1", NULL, "DMIC1 Power"}, + {"DMIC CLK", NULL, "DMIC ASRC"}, + + {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, + {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, + {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, + {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, + + {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, + {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, + {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, + {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, + + {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, + {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, + {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, + {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, + + {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, + {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, + {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, + + {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, + {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, + {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, + + {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, + {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, + + {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, + {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, + {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, + {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, + {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, + {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, + {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, + {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, + {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, + {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, + {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, + {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, + {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, + {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, + {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, + {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, + + {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, + {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, + {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, + {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, + {"IF1_ADC Mux", NULL, "I2S1"}, + {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, + {"AIF1TX", NULL, "ADCDAT Mux"}, + {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, + {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, + {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, + {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, + {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, + {"AIF2TX", NULL, "ADCDAT Mux"}, + + {"IF1 DAC1 L", NULL, "AIF1RX"}, + {"IF1 DAC1 L", NULL, "I2S1"}, + {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, + {"IF1 DAC1 R", NULL, "AIF1RX"}, + {"IF1 DAC1 R", NULL, "I2S1"}, + {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, + + {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, + {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"}, + {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, + {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"}, + + {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, + {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, + + {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, + {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, + + {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, + {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, + {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, + {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, + + {"DAC L1", NULL, "DAC L1 Source"}, + {"DAC R1", NULL, "DAC R1 Source"}, + + {"DAC L1", NULL, "DAC 1 Clock"}, + {"DAC R1", NULL, "DAC 1 Clock"}, + + {"HP Amp", NULL, "DAC L1"}, + {"HP Amp", NULL, "DAC R1"}, + {"HP Amp", NULL, "HP Amp L"}, + {"HP Amp", NULL, "HP Amp R"}, + {"HP Amp", NULL, "Capless"}, + {"HP Amp", NULL, "Charge Pump"}, + {"HP Amp", NULL, "CLKDET SYS"}, + {"HP Amp", NULL, "CBJ Power"}, + {"HP Amp", NULL, "Vref2"}, + {"HPOL Playback", "Switch", "HP Amp"}, + {"HPOR Playback", "Switch", "HP Amp"}, + {"HPOL", NULL, "HPOL Playback"}, + {"HPOR", NULL, "HPOR Playback"}, +}; + +static int rt5668_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, + unsigned int rx_mask, int slots, int slot_width) +{ + struct snd_soc_component *component = dai->component; + unsigned int val = 0; + + switch (slots) { + case 4: + val |= RT5668_TDM_TX_CH_4; + val |= RT5668_TDM_RX_CH_4; + break; + case 6: + val |= RT5668_TDM_TX_CH_6; + val |= RT5668_TDM_RX_CH_6; + break; + case 8: + val |= RT5668_TDM_TX_CH_8; + val |= RT5668_TDM_RX_CH_8; + break; + case 2: + break; + default: + return -EINVAL; + } + + snd_soc_component_update_bits(component, RT5668_TDM_CTRL, + RT5668_TDM_TX_CH_MASK | RT5668_TDM_RX_CH_MASK, val); + + switch (slot_width) { + case 16: + val = RT5668_TDM_CL_16; + break; + case 20: + val = RT5668_TDM_CL_20; + break; + case 24: + val = RT5668_TDM_CL_24; + break; + case 32: + val = RT5668_TDM_CL_32; + break; + default: + return -EINVAL; + } + + snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL, + RT5668_TDM_CL_MASK, val); + + return 0; +} + + +static int rt5668_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + unsigned int len_1 = 0, len_2 = 0; + int pre_div, frame_size; + + rt5668->lrck[dai->id] = params_rate(params); + pre_div = rl6231_get_clk_info(rt5668->sysclk, rt5668->lrck[dai->id]); + + frame_size = snd_soc_params_to_frame_size(params); + if (frame_size < 0) { + dev_err(component->dev, "Unsupported frame size: %d\n", + frame_size); + return -EINVAL; + } + + dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", + rt5668->lrck[dai->id], pre_div, dai->id); + + switch (params_width(params)) { + case 16: + break; + case 20: + len_1 |= RT5668_I2S1_DL_20; + len_2 |= RT5668_I2S2_DL_20; + break; + case 24: + len_1 |= RT5668_I2S1_DL_24; + len_2 |= RT5668_I2S2_DL_24; + break; + case 32: + len_1 |= RT5668_I2S1_DL_32; + len_2 |= RT5668_I2S2_DL_24; + break; + case 8: + len_1 |= RT5668_I2S2_DL_8; + len_2 |= RT5668_I2S2_DL_8; + break; + default: + return -EINVAL; + } + + switch (dai->id) { + case RT5668_AIF1: + snd_soc_component_update_bits(component, RT5668_I2S1_SDP, + RT5668_I2S1_DL_MASK, len_1); + if (rt5668->master[RT5668_AIF1]) { + snd_soc_component_update_bits(component, + RT5668_ADDA_CLK_1, RT5668_I2S_M_DIV_MASK, + pre_div << RT5668_I2S_M_DIV_SFT); + } + if (params_channels(params) == 1) /* mono mode */ + snd_soc_component_update_bits(component, + RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK, + RT5668_I2S1_MONO_EN); + else + snd_soc_component_update_bits(component, + RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK, + RT5668_I2S1_MONO_DIS); + break; + case RT5668_AIF2: + snd_soc_component_update_bits(component, RT5668_I2S2_SDP, + RT5668_I2S2_DL_MASK, len_2); + if (rt5668->master[RT5668_AIF2]) { + snd_soc_component_update_bits(component, + RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_M_PD_MASK, + pre_div << RT5668_I2S2_M_PD_SFT); + } + if (params_channels(params) == 1) /* mono mode */ + snd_soc_component_update_bits(component, + RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK, + RT5668_I2S2_MONO_EN); + else + snd_soc_component_update_bits(component, + RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK, + RT5668_I2S2_MONO_DIS); + break; + default: + dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); + return -EINVAL; + } + + return 0; +} + +static int rt5668_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_component *component = dai->component; + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + unsigned int reg_val = 0, tdm_ctrl = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + rt5668->master[dai->id] = 1; + break; + case SND_SOC_DAIFMT_CBS_CFS: + rt5668->master[dai->id] = 0; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + reg_val |= RT5668_I2S_BP_INV; + tdm_ctrl |= RT5668_TDM_S_BP_INV; + break; + case SND_SOC_DAIFMT_NB_IF: + if (dai->id == RT5668_AIF1) + tdm_ctrl |= RT5668_TDM_S_LP_INV | RT5668_TDM_M_BP_INV; + else + return -EINVAL; + break; + case SND_SOC_DAIFMT_IB_IF: + if (dai->id == RT5668_AIF1) + tdm_ctrl |= RT5668_TDM_S_BP_INV | RT5668_TDM_S_LP_INV | + RT5668_TDM_M_BP_INV | RT5668_TDM_M_LP_INV; + else + return -EINVAL; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + break; + case SND_SOC_DAIFMT_LEFT_J: + reg_val |= RT5668_I2S_DF_LEFT; + tdm_ctrl |= RT5668_TDM_DF_LEFT; + break; + case SND_SOC_DAIFMT_DSP_A: + reg_val |= RT5668_I2S_DF_PCM_A; + tdm_ctrl |= RT5668_TDM_DF_PCM_A; + break; + case SND_SOC_DAIFMT_DSP_B: + reg_val |= RT5668_I2S_DF_PCM_B; + tdm_ctrl |= RT5668_TDM_DF_PCM_B; + break; + default: + return -EINVAL; + } + + switch (dai->id) { + case RT5668_AIF1: + snd_soc_component_update_bits(component, RT5668_I2S1_SDP, + RT5668_I2S_DF_MASK, reg_val); + snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL, + RT5668_TDM_MS_MASK | RT5668_TDM_S_BP_MASK | + RT5668_TDM_DF_MASK | RT5668_TDM_M_BP_MASK | + RT5668_TDM_M_LP_MASK | RT5668_TDM_S_LP_MASK, + tdm_ctrl | rt5668->master[dai->id]); + break; + case RT5668_AIF2: + if (rt5668->master[dai->id] == 0) + reg_val |= RT5668_I2S2_MS_S; + snd_soc_component_update_bits(component, RT5668_I2S2_SDP, + RT5668_I2S2_MS_MASK | RT5668_I2S_BP_MASK | + RT5668_I2S_DF_MASK, reg_val); + break; + default: + dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); + return -EINVAL; + } + return 0; +} + +static int rt5668_set_component_sysclk(struct snd_soc_component *component, + int clk_id, int source, unsigned int freq, int dir) +{ + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + unsigned int reg_val = 0, src = 0; + + if (freq == rt5668->sysclk && clk_id == rt5668->sysclk_src) + return 0; + + switch (clk_id) { + case RT5668_SCLK_S_MCLK: + reg_val |= RT5668_SCLK_SRC_MCLK; + src = RT5668_CLK_SRC_MCLK; + break; + case RT5668_SCLK_S_PLL1: + reg_val |= RT5668_SCLK_SRC_PLL1; + src = RT5668_CLK_SRC_PLL1; + break; + case RT5668_SCLK_S_PLL2: + reg_val |= RT5668_SCLK_SRC_PLL2; + src = RT5668_CLK_SRC_PLL2; + break; + case RT5668_SCLK_S_RCCLK: + reg_val |= RT5668_SCLK_SRC_RCCLK; + src = RT5668_CLK_SRC_RCCLK; + break; + default: + dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); + return -EINVAL; + } + snd_soc_component_update_bits(component, RT5668_GLB_CLK, + RT5668_SCLK_SRC_MASK, reg_val); + + if (rt5668->master[RT5668_AIF2]) { + snd_soc_component_update_bits(component, + RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_SRC_MASK, + src << RT5668_I2S2_SRC_SFT); + } + + rt5668->sysclk = freq; + rt5668->sysclk_src = clk_id; + + dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", + freq, clk_id); + + return 0; +} + +static int rt5668_set_component_pll(struct snd_soc_component *component, + int pll_id, int source, unsigned int freq_in, + unsigned int freq_out) +{ + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + struct rl6231_pll_code pll_code; + int ret; + + if (source == rt5668->pll_src && freq_in == rt5668->pll_in && + freq_out == rt5668->pll_out) + return 0; + + if (!freq_in || !freq_out) { + dev_dbg(component->dev, "PLL disabled\n"); + + rt5668->pll_in = 0; + rt5668->pll_out = 0; + snd_soc_component_update_bits(component, RT5668_GLB_CLK, + RT5668_SCLK_SRC_MASK, RT5668_SCLK_SRC_MCLK); + return 0; + } + + switch (source) { + case RT5668_PLL1_S_MCLK: + snd_soc_component_update_bits(component, RT5668_GLB_CLK, + RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_MCLK); + break; + case RT5668_PLL1_S_BCLK1: + snd_soc_component_update_bits(component, RT5668_GLB_CLK, + RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_BCLK1); + break; + default: + dev_err(component->dev, "Unknown PLL Source %d\n", source); + return -EINVAL; + } + + ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); + if (ret < 0) { + dev_err(component->dev, "Unsupport input clock %d\n", freq_in); + return ret; + } + + dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", + pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), + pll_code.n_code, pll_code.k_code); + + snd_soc_component_write(component, RT5668_PLL_CTRL_1, + pll_code.n_code << RT5668_PLL_N_SFT | pll_code.k_code); + snd_soc_component_write(component, RT5668_PLL_CTRL_2, + (pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SFT | + pll_code.m_bp << RT5668_PLL_M_BP_SFT); + + rt5668->pll_in = freq_in; + rt5668->pll_out = freq_out; + rt5668->pll_src = source; + + return 0; +} + +static int rt5668_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) +{ + struct snd_soc_component *component = dai->component; + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + + rt5668->bclk[dai->id] = ratio; + + switch (ratio) { + case 64: + snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2, + RT5668_I2S2_BCLK_MS2_MASK, + RT5668_I2S2_BCLK_MS2_64); + break; + case 32: + snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2, + RT5668_I2S2_BCLK_MS2_MASK, + RT5668_I2S2_BCLK_MS2_32); + break; + default: + dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio); + return -EINVAL; + } + + return 0; +} + +static int rt5668_set_bias_level(struct snd_soc_component *component, + enum snd_soc_bias_level level) +{ + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + + switch (level) { + case SND_SOC_BIAS_PREPARE: + regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, + RT5668_PWR_MB | RT5668_PWR_BG, + RT5668_PWR_MB | RT5668_PWR_BG); + regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, + RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, + RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO); + break; + + case SND_SOC_BIAS_STANDBY: + regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, + RT5668_PWR_MB, RT5668_PWR_MB); + regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, + RT5668_DIG_GATE_CTRL, RT5668_DIG_GATE_CTRL); + break; + case SND_SOC_BIAS_OFF: + regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, + RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 0); + regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, + RT5668_PWR_MB | RT5668_PWR_BG, 0); + break; + + default: + break; + } + + return 0; +} + +static int rt5668_probe(struct snd_soc_component *component) +{ + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + + rt5668->component = component; + + return 0; +} + +static void rt5668_remove(struct snd_soc_component *component) +{ + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + + rt5668_reset(rt5668->regmap); +} + +#ifdef CONFIG_PM +static int rt5668_suspend(struct snd_soc_component *component) +{ + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + + regcache_cache_only(rt5668->regmap, true); + regcache_mark_dirty(rt5668->regmap); + return 0; +} + +static int rt5668_resume(struct snd_soc_component *component) +{ + struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); + + regcache_cache_only(rt5668->regmap, false); + regcache_sync(rt5668->regmap); + + return 0; +} +#else +#define rt5668_suspend NULL +#define rt5668_resume NULL +#endif + +#define RT5668_STEREO_RATES SNDRV_PCM_RATE_8000_192000 +#define RT5668_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) + +static const struct snd_soc_dai_ops rt5668_aif1_dai_ops = { + .hw_params = rt5668_hw_params, + .set_fmt = rt5668_set_dai_fmt, + .set_tdm_slot = rt5668_set_tdm_slot, +}; + +static const struct snd_soc_dai_ops rt5668_aif2_dai_ops = { + .hw_params = rt5668_hw_params, + .set_fmt = rt5668_set_dai_fmt, + .set_bclk_ratio = rt5668_set_bclk_ratio, +}; + +static struct snd_soc_dai_driver rt5668_dai[] = { + { + .name = "rt5668-aif1", + .id = RT5668_AIF1, + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT5668_STEREO_RATES, + .formats = RT5668_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT5668_STEREO_RATES, + .formats = RT5668_FORMATS, + }, + .ops = &rt5668_aif1_dai_ops, + }, + { + .name = "rt5668-aif2", + .id = RT5668_AIF2, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT5668_STEREO_RATES, + .formats = RT5668_FORMATS, + }, + .ops = &rt5668_aif2_dai_ops, + }, +}; + +static const struct snd_soc_component_driver soc_component_dev_rt5668 = { + .probe = rt5668_probe, + .remove = rt5668_remove, + .suspend = rt5668_suspend, + .resume = rt5668_resume, + .set_bias_level = rt5668_set_bias_level, + .controls = rt5668_snd_controls, + .num_controls = ARRAY_SIZE(rt5668_snd_controls), + .dapm_widgets = rt5668_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rt5668_dapm_widgets), + .dapm_routes = rt5668_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rt5668_dapm_routes), + .set_sysclk = rt5668_set_component_sysclk, + .set_pll = rt5668_set_component_pll, + .set_jack = rt5668_set_jack_detect, + .use_pmdown_time = 1, + .endianness = 1, + .non_legacy_dai_naming = 1, +}; + +static const struct regmap_config rt5668_regmap = { + .reg_bits = 16, + .val_bits = 16, + .max_register = RT5668_I2C_MODE, + .volatile_reg = rt5668_volatile_register, + .readable_reg = rt5668_readable_register, + .cache_type = REGCACHE_RBTREE, + .reg_defaults = rt5668_reg, + .num_reg_defaults = ARRAY_SIZE(rt5668_reg), + .use_single_rw = true, +}; + +static const struct i2c_device_id rt5668_i2c_id[] = { + {"rt5668b", 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, rt5668_i2c_id); + +static int rt5668_parse_dt(struct rt5668_priv *rt5668, struct device *dev) +{ + + of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin", + &rt5668->pdata.dmic1_data_pin); + of_property_read_u32(dev->of_node, "realtek,dmic1-clk-pin", + &rt5668->pdata.dmic1_clk_pin); + of_property_read_u32(dev->of_node, "realtek,jd-src", + &rt5668->pdata.jd_src); + + rt5668->pdata.ldo1_en = of_get_named_gpio(dev->of_node, + "realtek,ldo1-en-gpios", 0); + + return 0; +} + +static void rt5668_calibrate(struct rt5668_priv *rt5668) +{ + int value, count; + + mutex_lock(&rt5668->calibrate_mutex); + + rt5668_reset(rt5668->regmap); + regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xa2bf); + usleep_range(15000, 20000); + regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xf2bf); + regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380); + regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8001); + regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000); + regmap_write(rt5668->regmap, RT5668_STO1_DAC_MIXER, 0x2080); + regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x4040); + regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0069); + regmap_write(rt5668->regmap, RT5668_CHOP_DAC, 0x3000); + regmap_write(rt5668->regmap, RT5668_HP_CTRL_2, 0x6000); + regmap_write(rt5668->regmap, RT5668_HP_CHARGE_PUMP_1, 0x0f26); + regmap_write(rt5668->regmap, RT5668_CALIB_ADC_CTRL, 0x7f05); + regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x686c); + regmap_write(rt5668->regmap, RT5668_CAL_REC, 0x0d0d); + regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_9, 0x000f); + regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8d01); + regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_2, 0x0321); + regmap_write(rt5668->regmap, RT5668_HP_LOGIC_CTRL_2, 0x0004); + regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0x7c00); + regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_3, 0x06a1); + regmap_write(rt5668->regmap, RT5668_A_DAC1_MUX, 0x0311); + regmap_write(rt5668->regmap, RT5668_RESET_HPF_CTRL, 0x0000); + regmap_write(rt5668->regmap, RT5668_ADC_STO1_HP_CTRL_1, 0x3320); + + regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0xfc00); + + for (count = 0; count < 60; count++) { + regmap_read(rt5668->regmap, RT5668_HP_CALIB_STA_1, &value); + if (!(value & 0x8000)) + break; + + usleep_range(10000, 10005); + } + + if (count >= 60) + pr_err("HP Calibration Failure\n"); + + /* restore settings */ + regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0xc0c4); + regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x0000); + + mutex_unlock(&rt5668->calibrate_mutex); + +} + +static int rt5668_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct rt5668_platform_data *pdata = dev_get_platdata(&i2c->dev); + struct rt5668_priv *rt5668; + int i, ret; + unsigned int val; + + rt5668 = devm_kzalloc(&i2c->dev, sizeof(struct rt5668_priv), + GFP_KERNEL); + + if (rt5668 == NULL) + return -ENOMEM; + + i2c_set_clientdata(i2c, rt5668); + + if (pdata) + rt5668->pdata = *pdata; + else + rt5668_parse_dt(rt5668, &i2c->dev); + + rt5668->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap); + if (IS_ERR(rt5668->regmap)) { + ret = PTR_ERR(rt5668->regmap); + dev_err(&i2c->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(rt5668->supplies); i++) + rt5668->supplies[i].supply = rt5668_supply_names[i]; + + ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5668->supplies), + rt5668->supplies); + if (ret != 0) { + dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); + return ret; + } + + ret = regulator_bulk_enable(ARRAY_SIZE(rt5668->supplies), + rt5668->supplies); + if (ret != 0) { + dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); + return ret; + } + + if (gpio_is_valid(rt5668->pdata.ldo1_en)) { + if (devm_gpio_request_one(&i2c->dev, rt5668->pdata.ldo1_en, + GPIOF_OUT_INIT_HIGH, "rt5668")) + dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n"); + } + + /* Sleep for 300 ms miniumum */ + usleep_range(300000, 350000); + + regmap_write(rt5668->regmap, RT5668_I2C_MODE, 0x1); + usleep_range(10000, 15000); + + regmap_read(rt5668->regmap, RT5668_DEVICE_ID, &val); + if (val != DEVICE_ID) { + pr_err("Device with ID register %x is not rt5668\n", val); + return -ENODEV; + } + + rt5668_reset(rt5668->regmap); + + rt5668_calibrate(rt5668); + + regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0000); + + /* DMIC pin*/ + if (rt5668->pdata.dmic1_data_pin != RT5668_DMIC1_NULL) { + switch (rt5668->pdata.dmic1_data_pin) { + case RT5668_DMIC1_DATA_GPIO2: /* share with LRCK2 */ + regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1, + RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO2); + regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, + RT5668_GP2_PIN_MASK, RT5668_GP2_PIN_DMIC_SDA); + break; + + case RT5668_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ + regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1, + RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO5); + regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, + RT5668_GP5_PIN_MASK, RT5668_GP5_PIN_DMIC_SDA); + break; + + default: + dev_dbg(&i2c->dev, "invalid DMIC_DAT pin\n"); + break; + } + + switch (rt5668->pdata.dmic1_clk_pin) { + case RT5668_DMIC1_CLK_GPIO1: /* share with IRQ */ + regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, + RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_DMIC_CLK); + break; + + case RT5668_DMIC1_CLK_GPIO3: /* share with BCLK2 */ + regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, + RT5668_GP3_PIN_MASK, RT5668_GP3_PIN_DMIC_CLK); + break; + + default: + dev_dbg(&i2c->dev, "invalid DMIC_CLK pin\n"); + break; + } + } + + regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, + RT5668_LDO1_DVO_MASK | RT5668_HP_DRIVER_MASK, + RT5668_LDO1_DVO_14 | RT5668_HP_DRIVER_5X); + regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380); + regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, + RT5668_GP4_PIN_MASK | RT5668_GP5_PIN_MASK, + RT5668_GP4_PIN_ADCDAT1 | RT5668_GP5_PIN_DACDAT1); + regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000); + + INIT_DELAYED_WORK(&rt5668->jack_detect_work, + rt5668_jack_detect_handler); + INIT_DELAYED_WORK(&rt5668->jd_check_work, + rt5668_jd_check_handler); + + mutex_init(&rt5668->calibrate_mutex); + + if (i2c->irq) { + ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, + rt5668_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING + | IRQF_ONESHOT, "rt5668", rt5668); + if (ret) + dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); + + } + + return snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5668, + rt5668_dai, ARRAY_SIZE(rt5668_dai)); +} + +static int rt5668_i2c_remove(struct i2c_client *i2c) +{ + snd_soc_unregister_component(&i2c->dev); + + return 0; +} + +static void rt5668_i2c_shutdown(struct i2c_client *client) +{ + struct rt5668_priv *rt5668 = i2c_get_clientdata(client); + + rt5668_reset(rt5668->regmap); +} + +#ifdef CONFIG_OF +static const struct of_device_id rt5668_of_match[] = { + {.compatible = "realtek,rt5668b"}, + {}, +}; +MODULE_DEVICE_TABLE(of, rt5668_of_match); +#endif + +#ifdef CONFIG_ACPI +static const struct acpi_device_id rt5668_acpi_match[] = { + {"10EC5668", 0,}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, rt5668_acpi_match); +#endif + +static struct i2c_driver rt5668_i2c_driver = { + .driver = { + .name = "rt5668b", + .of_match_table = of_match_ptr(rt5668_of_match), + .acpi_match_table = ACPI_PTR(rt5668_acpi_match), + }, + .probe = rt5668_i2c_probe, + .remove = rt5668_i2c_remove, + .shutdown = rt5668_i2c_shutdown, + .id_table = rt5668_i2c_id, +}; +module_i2c_driver(rt5668_i2c_driver); + +MODULE_DESCRIPTION("ASoC RT5668B driver"); +MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/rt5668.h b/sound/soc/codecs/rt5668.h new file mode 100644 index 000000000000..3e7bcfd569ec --- /dev/null +++ b/sound/soc/codecs/rt5668.h @@ -0,0 +1,1318 @@ +/* + * rt5668.h -- RT5668/RT5658 ALSA SoC audio driver + * + * Copyright 2018 Realtek Microelectronics + * Author: Bard Liao <bardliao@realtek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __RT5668_H__ +#define __RT5668_H__ + +#include <sound/rt5668.h> + +#define DEVICE_ID 0x6530 + +/* Info */ +#define RT5668_RESET 0x0000 +#define RT5668_VERSION_ID 0x00fd +#define RT5668_VENDOR_ID 0x00fe +#define RT5668_DEVICE_ID 0x00ff +/* I/O - Output */ +#define RT5668_HP_CTRL_1 0x0002 +#define RT5668_HP_CTRL_2 0x0003 +#define RT5668_HPL_GAIN 0x0005 +#define RT5668_HPR_GAIN 0x0006 + +#define RT5668_I2C_CTRL 0x0008 + +/* I/O - Input */ +#define RT5668_CBJ_BST_CTRL 0x000b +#define RT5668_CBJ_CTRL_1 0x0010 +#define RT5668_CBJ_CTRL_2 0x0011 +#define RT5668_CBJ_CTRL_3 0x0012 +#define RT5668_CBJ_CTRL_4 0x0013 +#define RT5668_CBJ_CTRL_5 0x0014 +#define RT5668_CBJ_CTRL_6 0x0015 +#define RT5668_CBJ_CTRL_7 0x0016 +/* I/O - ADC/DAC/DMIC */ +#define RT5668_DAC1_DIG_VOL 0x0019 +#define RT5668_STO1_ADC_DIG_VOL 0x001c +#define RT5668_STO1_ADC_BOOST 0x001f +#define RT5668_HP_IMP_GAIN_1 0x0022 +#define RT5668_HP_IMP_GAIN_2 0x0023 +/* Mixer - D-D */ +#define RT5668_SIDETONE_CTRL 0x0024 +#define RT5668_STO1_ADC_MIXER 0x0026 +#define RT5668_AD_DA_MIXER 0x0029 +#define RT5668_STO1_DAC_MIXER 0x002a +#define RT5668_A_DAC1_MUX 0x002b +#define RT5668_DIG_INF2_DATA 0x0030 +/* Mixer - ADC */ +#define RT5668_REC_MIXER 0x003c +#define RT5668_CAL_REC 0x0044 +#define RT5668_ALC_BACK_GAIN 0x0049 +/* Power */ +#define RT5668_PWR_DIG_1 0x0061 +#define RT5668_PWR_DIG_2 0x0062 +#define RT5668_PWR_ANLG_1 0x0063 +#define RT5668_PWR_ANLG_2 0x0064 +#define RT5668_PWR_ANLG_3 0x0065 +#define RT5668_PWR_MIXER 0x0066 +#define RT5668_PWR_VOL 0x0067 +/* Clock Detect */ +#define RT5668_CLK_DET 0x006b +/* Filter Auto Reset */ +#define RT5668_RESET_LPF_CTRL 0x006c +#define RT5668_RESET_HPF_CTRL 0x006d +/* DMIC */ +#define RT5668_DMIC_CTRL_1 0x006e +/* Format - ADC/DAC */ +#define RT5668_I2S1_SDP 0x0070 +#define RT5668_I2S2_SDP 0x0071 +#define RT5668_ADDA_CLK_1 0x0073 +#define RT5668_ADDA_CLK_2 0x0074 +#define RT5668_I2S1_F_DIV_CTRL_1 0x0075 +#define RT5668_I2S1_F_DIV_CTRL_2 0x0076 +/* Format - TDM Control */ +#define RT5668_TDM_CTRL 0x0079 +#define RT5668_TDM_ADDA_CTRL_1 0x007a +#define RT5668_TDM_ADDA_CTRL_2 0x007b +#define RT5668_DATA_SEL_CTRL_1 0x007c +#define RT5668_TDM_TCON_CTRL 0x007e +/* Function - Analog */ +#define RT5668_GLB_CLK 0x0080 +#define RT5668_PLL_CTRL_1 0x0081 +#define RT5668_PLL_CTRL_2 0x0082 +#define RT5668_PLL_TRACK_1 0x0083 +#define RT5668_PLL_TRACK_2 0x0084 +#define RT5668_PLL_TRACK_3 0x0085 +#define RT5668_PLL_TRACK_4 0x0086 +#define RT5668_PLL_TRACK_5 0x0087 +#define RT5668_PLL_TRACK_6 0x0088 +#define RT5668_PLL_TRACK_11 0x008c +#define RT5668_SDW_REF_CLK 0x008d +#define RT5668_DEPOP_1 0x008e +#define RT5668_DEPOP_2 0x008f +#define RT5668_HP_CHARGE_PUMP_1 0x0091 +#define RT5668_HP_CHARGE_PUMP_2 0x0092 +#define RT5668_MICBIAS_1 0x0093 +#define RT5668_MICBIAS_2 0x0094 +#define RT5668_PLL_TRACK_12 0x0098 +#define RT5668_PLL_TRACK_14 0x009a +#define RT5668_PLL2_CTRL_1 0x009b +#define RT5668_PLL2_CTRL_2 0x009c +#define RT5668_PLL2_CTRL_3 0x009d +#define RT5668_PLL2_CTRL_4 0x009e +#define RT5668_RC_CLK_CTRL 0x009f +#define RT5668_I2S_M_CLK_CTRL_1 0x00a0 +#define RT5668_I2S2_F_DIV_CTRL_1 0x00a3 +#define RT5668_I2S2_F_DIV_CTRL_2 0x00a4 +/* Function - Digital */ +#define RT5668_EQ_CTRL_1 0x00ae +#define RT5668_EQ_CTRL_2 0x00af +#define RT5668_IRQ_CTRL_1 0x00b6 +#define RT5668_IRQ_CTRL_2 0x00b7 +#define RT5668_IRQ_CTRL_3 0x00b8 +#define RT5668_IRQ_CTRL_4 0x00b9 +#define RT5668_INT_ST_1 0x00be +#define RT5668_GPIO_CTRL_1 0x00c0 +#define RT5668_GPIO_CTRL_2 0x00c1 +#define RT5668_GPIO_CTRL_3 0x00c2 +#define RT5668_HP_AMP_DET_CTRL_1 0x00d0 +#define RT5668_HP_AMP_DET_CTRL_2 0x00d1 +#define RT5668_MID_HP_AMP_DET 0x00d2 +#define RT5668_LOW_HP_AMP_DET 0x00d3 +#define RT5668_DELAY_BUF_CTRL 0x00d4 +#define RT5668_SV_ZCD_1 0x00d9 +#define RT5668_SV_ZCD_2 0x00da +#define RT5668_IL_CMD_1 0x00db +#define RT5668_IL_CMD_2 0x00dc +#define RT5668_IL_CMD_3 0x00dd +#define RT5668_IL_CMD_4 0x00de +#define RT5668_IL_CMD_5 0x00df +#define RT5668_IL_CMD_6 0x00e0 +#define RT5668_4BTN_IL_CMD_1 0x00e2 +#define RT5668_4BTN_IL_CMD_2 0x00e3 +#define RT5668_4BTN_IL_CMD_3 0x00e4 +#define RT5668_4BTN_IL_CMD_4 0x00e5 +#define RT5668_4BTN_IL_CMD_5 0x00e6 +#define RT5668_4BTN_IL_CMD_6 0x00e7 +#define RT5668_4BTN_IL_CMD_7 0x00e8 + +#define RT5668_ADC_STO1_HP_CTRL_1 0x00ea +#define RT5668_ADC_STO1_HP_CTRL_2 0x00eb +#define RT5668_AJD1_CTRL 0x00f0 +#define RT5668_JD1_THD 0x00f1 +#define RT5668_JD2_THD 0x00f2 +#define RT5668_JD_CTRL_1 0x00f6 +/* General Control */ +#define RT5668_DUMMY_1 0x00fa +#define RT5668_DUMMY_2 0x00fb +#define RT5668_DUMMY_3 0x00fc + +#define RT5668_DAC_ADC_DIG_VOL1 0x0100 +#define RT5668_BIAS_CUR_CTRL_2 0x010b +#define RT5668_BIAS_CUR_CTRL_3 0x010c +#define RT5668_BIAS_CUR_CTRL_4 0x010d +#define RT5668_BIAS_CUR_CTRL_5 0x010e +#define RT5668_BIAS_CUR_CTRL_6 0x010f +#define RT5668_BIAS_CUR_CTRL_7 0x0110 +#define RT5668_BIAS_CUR_CTRL_8 0x0111 +#define RT5668_BIAS_CUR_CTRL_9 0x0112 +#define RT5668_BIAS_CUR_CTRL_10 0x0113 +#define RT5668_VREF_REC_OP_FB_CAP_CTRL 0x0117 +#define RT5668_CHARGE_PUMP_1 0x0125 +#define RT5668_DIG_IN_CTRL_1 0x0132 +#define RT5668_PAD_DRIVING_CTRL 0x0136 +#define RT5668_SOFT_RAMP_DEPOP 0x0138 +#define RT5668_CHOP_DAC 0x013a +#define RT5668_CHOP_ADC 0x013b +#define RT5668_CALIB_ADC_CTRL 0x013c +#define RT5668_VOL_TEST 0x013f +#define RT5668_SPKVDD_DET_STA 0x0142 +#define RT5668_TEST_MODE_CTRL_1 0x0145 +#define RT5668_TEST_MODE_CTRL_2 0x0146 +#define RT5668_TEST_MODE_CTRL_3 0x0147 +#define RT5668_TEST_MODE_CTRL_4 0x0148 +#define RT5668_TEST_MODE_CTRL_5 0x0149 +#define RT5668_PLL1_INTERNAL 0x0150 +#define RT5668_PLL2_INTERNAL 0x0151 +#define RT5668_STO_NG2_CTRL_1 0x0160 +#define RT5668_STO_NG2_CTRL_2 0x0161 +#define RT5668_STO_NG2_CTRL_3 0x0162 +#define RT5668_STO_NG2_CTRL_4 0x0163 +#define RT5668_STO_NG2_CTRL_5 0x0164 +#define RT5668_STO_NG2_CTRL_6 0x0165 +#define RT5668_STO_NG2_CTRL_7 0x0166 +#define RT5668_STO_NG2_CTRL_8 0x0167 +#define RT5668_STO_NG2_CTRL_9 0x0168 +#define RT5668_STO_NG2_CTRL_10 0x0169 +#define RT5668_STO1_DAC_SIL_DET 0x0190 +#define RT5668_SIL_PSV_CTRL1 0x0194 +#define RT5668_SIL_PSV_CTRL2 0x0195 +#define RT5668_SIL_PSV_CTRL3 0x0197 +#define RT5668_SIL_PSV_CTRL4 0x0198 +#define RT5668_SIL_PSV_CTRL5 0x0199 +#define RT5668_HP_IMP_SENS_CTRL_01 0x01af +#define RT5668_HP_IMP_SENS_CTRL_02 0x01b0 +#define RT5668_HP_IMP_SENS_CTRL_03 0x01b1 +#define RT5668_HP_IMP_SENS_CTRL_04 0x01b2 +#define RT5668_HP_IMP_SENS_CTRL_05 0x01b3 +#define RT5668_HP_IMP_SENS_CTRL_06 0x01b4 +#define RT5668_HP_IMP_SENS_CTRL_07 0x01b5 +#define RT5668_HP_IMP_SENS_CTRL_08 0x01b6 +#define RT5668_HP_IMP_SENS_CTRL_09 0x01b7 +#define RT5668_HP_IMP_SENS_CTRL_10 0x01b8 +#define RT5668_HP_IMP_SENS_CTRL_11 0x01b9 +#define RT5668_HP_IMP_SENS_CTRL_12 0x01ba +#define RT5668_HP_IMP_SENS_CTRL_13 0x01bb +#define RT5668_HP_IMP_SENS_CTRL_14 0x01bc +#define RT5668_HP_IMP_SENS_CTRL_15 0x01bd +#define RT5668_HP_IMP_SENS_CTRL_16 0x01be +#define RT5668_HP_IMP_SENS_CTRL_17 0x01bf +#define RT5668_HP_IMP_SENS_CTRL_18 0x01c0 +#define RT5668_HP_IMP_SENS_CTRL_19 0x01c1 +#define RT5668_HP_IMP_SENS_CTRL_20 0x01c2 +#define RT5668_HP_IMP_SENS_CTRL_21 0x01c3 +#define RT5668_HP_IMP_SENS_CTRL_22 0x01c4 +#define RT5668_HP_IMP_SENS_CTRL_23 0x01c5 +#define RT5668_HP_IMP_SENS_CTRL_24 0x01c6 +#define RT5668_HP_IMP_SENS_CTRL_25 0x01c7 +#define RT5668_HP_IMP_SENS_CTRL_26 0x01c8 +#define RT5668_HP_IMP_SENS_CTRL_27 0x01c9 +#define RT5668_HP_IMP_SENS_CTRL_28 0x01ca +#define RT5668_HP_IMP_SENS_CTRL_29 0x01cb +#define RT5668_HP_IMP_SENS_CTRL_30 0x01cc +#define RT5668_HP_IMP_SENS_CTRL_31 0x01cd +#define RT5668_HP_IMP_SENS_CTRL_32 0x01ce +#define RT5668_HP_IMP_SENS_CTRL_33 0x01cf +#define RT5668_HP_IMP_SENS_CTRL_34 0x01d0 +#define RT5668_HP_IMP_SENS_CTRL_35 0x01d1 +#define RT5668_HP_IMP_SENS_CTRL_36 0x01d2 +#define RT5668_HP_IMP_SENS_CTRL_37 0x01d3 +#define RT5668_HP_IMP_SENS_CTRL_38 0x01d4 +#define RT5668_HP_IMP_SENS_CTRL_39 0x01d5 +#define RT5668_HP_IMP_SENS_CTRL_40 0x01d6 +#define RT5668_HP_IMP_SENS_CTRL_41 0x01d7 +#define RT5668_HP_IMP_SENS_CTRL_42 0x01d8 +#define RT5668_HP_IMP_SENS_CTRL_43 0x01d9 +#define RT5668_HP_LOGIC_CTRL_1 0x01da +#define RT5668_HP_LOGIC_CTRL_2 0x01db +#define RT5668_HP_LOGIC_CTRL_3 0x01dc +#define RT5668_HP_CALIB_CTRL_1 0x01de +#define RT5668_HP_CALIB_CTRL_2 0x01df +#define RT5668_HP_CALIB_CTRL_3 0x01e0 +#define RT5668_HP_CALIB_CTRL_4 0x01e1 +#define RT5668_HP_CALIB_CTRL_5 0x01e2 +#define RT5668_HP_CALIB_CTRL_6 0x01e3 +#define RT5668_HP_CALIB_CTRL_7 0x01e4 +#define RT5668_HP_CALIB_CTRL_9 0x01e6 +#define RT5668_HP_CALIB_CTRL_10 0x01e7 +#define RT5668_HP_CALIB_CTRL_11 0x01e8 +#define RT5668_HP_CALIB_STA_1 0x01ea +#define RT5668_HP_CALIB_STA_2 0x01eb +#define RT5668_HP_CALIB_STA_3 0x01ec +#define RT5668_HP_CALIB_STA_4 0x01ed +#define RT5668_HP_CALIB_STA_5 0x01ee +#define RT5668_HP_CALIB_STA_6 0x01ef +#define RT5668_HP_CALIB_STA_7 0x01f0 +#define RT5668_HP_CALIB_STA_8 0x01f1 +#define RT5668_HP_CALIB_STA_9 0x01f2 +#define RT5668_HP_CALIB_STA_10 0x01f3 +#define RT5668_HP_CALIB_STA_11 0x01f4 +#define RT5668_SAR_IL_CMD_1 0x0210 +#define RT5668_SAR_IL_CMD_2 0x0211 +#define RT5668_SAR_IL_CMD_3 0x0212 +#define RT5668_SAR_IL_CMD_4 0x0213 +#define RT5668_SAR_IL_CMD_5 0x0214 +#define RT5668_SAR_IL_CMD_6 0x0215 +#define RT5668_SAR_IL_CMD_7 0x0216 +#define RT5668_SAR_IL_CMD_8 0x0217 +#define RT5668_SAR_IL_CMD_9 0x0218 +#define RT5668_SAR_IL_CMD_10 0x0219 +#define RT5668_SAR_IL_CMD_11 0x021a +#define RT5668_SAR_IL_CMD_12 0x021b +#define RT5668_SAR_IL_CMD_13 0x021c +#define RT5668_EFUSE_CTRL_1 0x0250 +#define RT5668_EFUSE_CTRL_2 0x0251 +#define RT5668_EFUSE_CTRL_3 0x0252 +#define RT5668_EFUSE_CTRL_4 0x0253 +#define RT5668_EFUSE_CTRL_5 0x0254 +#define RT5668_EFUSE_CTRL_6 0x0255 +#define RT5668_EFUSE_CTRL_7 0x0256 +#define RT5668_EFUSE_CTRL_8 0x0257 +#define RT5668_EFUSE_CTRL_9 0x0258 +#define RT5668_EFUSE_CTRL_10 0x0259 +#define RT5668_EFUSE_CTRL_11 0x025a +#define RT5668_JD_TOP_VC_VTRL 0x0270 +#define RT5668_DRC1_CTRL_0 0x02ff +#define RT5668_DRC1_CTRL_1 0x0300 +#define RT5668_DRC1_CTRL_2 0x0301 +#define RT5668_DRC1_CTRL_3 0x0302 +#define RT5668_DRC1_CTRL_4 0x0303 +#define RT5668_DRC1_CTRL_5 0x0304 +#define RT5668_DRC1_CTRL_6 0x0305 +#define RT5668_DRC1_HARD_LMT_CTRL_1 0x0306 +#define RT5668_DRC1_HARD_LMT_CTRL_2 0x0307 +#define RT5668_DRC1_PRIV_1 0x0310 +#define RT5668_DRC1_PRIV_2 0x0311 +#define RT5668_DRC1_PRIV_3 0x0312 +#define RT5668_DRC1_PRIV_4 0x0313 +#define RT5668_DRC1_PRIV_5 0x0314 +#define RT5668_DRC1_PRIV_6 0x0315 +#define RT5668_DRC1_PRIV_7 0x0316 +#define RT5668_DRC1_PRIV_8 0x0317 +#define RT5668_EQ_AUTO_RCV_CTRL1 0x03c0 +#define RT5668_EQ_AUTO_RCV_CTRL2 0x03c1 +#define RT5668_EQ_AUTO_RCV_CTRL3 0x03c2 +#define RT5668_EQ_AUTO_RCV_CTRL4 0x03c3 +#define RT5668_EQ_AUTO_RCV_CTRL5 0x03c4 +#define RT5668_EQ_AUTO_RCV_CTRL6 0x03c5 +#define RT5668_EQ_AUTO_RCV_CTRL7 0x03c6 +#define RT5668_EQ_AUTO_RCV_CTRL8 0x03c7 +#define RT5668_EQ_AUTO_RCV_CTRL9 0x03c8 +#define RT5668_EQ_AUTO_RCV_CTRL10 0x03c9 +#define RT5668_EQ_AUTO_RCV_CTRL11 0x03ca +#define RT5668_EQ_AUTO_RCV_CTRL12 0x03cb +#define RT5668_EQ_AUTO_RCV_CTRL13 0x03cc +#define RT5668_ADC_L_EQ_LPF1_A1 0x03d0 +#define RT5668_R_EQ_LPF1_A1 0x03d1 +#define RT5668_L_EQ_LPF1_H0 0x03d2 +#define RT5668_R_EQ_LPF1_H0 0x03d3 +#define RT5668_L_EQ_BPF1_A1 0x03d4 +#define RT5668_R_EQ_BPF1_A1 0x03d5 +#define RT5668_L_EQ_BPF1_A2 0x03d6 +#define RT5668_R_EQ_BPF1_A2 0x03d7 +#define RT5668_L_EQ_BPF1_H0 0x03d8 +#define RT5668_R_EQ_BPF1_H0 0x03d9 +#define RT5668_L_EQ_BPF2_A1 0x03da +#define RT5668_R_EQ_BPF2_A1 0x03db +#define RT5668_L_EQ_BPF2_A2 0x03dc +#define RT5668_R_EQ_BPF2_A2 0x03dd +#define RT5668_L_EQ_BPF2_H0 0x03de +#define RT5668_R_EQ_BPF2_H0 0x03df +#define RT5668_L_EQ_BPF3_A1 0x03e0 +#define RT5668_R_EQ_BPF3_A1 0x03e1 +#define RT5668_L_EQ_BPF3_A2 0x03e2 +#define RT5668_R_EQ_BPF3_A2 0x03e3 +#define RT5668_L_EQ_BPF3_H0 0x03e4 +#define RT5668_R_EQ_BPF3_H0 0x03e5 +#define RT5668_L_EQ_BPF4_A1 0x03e6 +#define RT5668_R_EQ_BPF4_A1 0x03e7 +#define RT5668_L_EQ_BPF4_A2 0x03e8 +#define RT5668_R_EQ_BPF4_A2 0x03e9 +#define RT5668_L_EQ_BPF4_H0 0x03ea +#define RT5668_R_EQ_BPF4_H0 0x03eb +#define RT5668_L_EQ_HPF1_A1 0x03ec +#define RT5668_R_EQ_HPF1_A1 0x03ed +#define RT5668_L_EQ_HPF1_H0 0x03ee +#define RT5668_R_EQ_HPF1_H0 0x03ef +#define RT5668_L_EQ_PRE_VOL 0x03f0 +#define RT5668_R_EQ_PRE_VOL 0x03f1 +#define RT5668_L_EQ_POST_VOL 0x03f2 +#define RT5668_R_EQ_POST_VOL 0x03f3 +#define RT5668_I2C_MODE 0xffff + + +/* global definition */ +#define RT5668_L_MUTE (0x1 << 15) +#define RT5668_L_MUTE_SFT 15 +#define RT5668_VOL_L_MUTE (0x1 << 14) +#define RT5668_VOL_L_SFT 14 +#define RT5668_R_MUTE (0x1 << 7) +#define RT5668_R_MUTE_SFT 7 +#define RT5668_VOL_R_MUTE (0x1 << 6) +#define RT5668_VOL_R_SFT 6 +#define RT5668_L_VOL_MASK (0x3f << 8) +#define RT5668_L_VOL_SFT 8 +#define RT5668_R_VOL_MASK (0x3f) +#define RT5668_R_VOL_SFT 0 + +/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ +#define RT5668_G_HP (0xf << 8) +#define RT5668_G_HP_SFT 8 +#define RT5668_G_STO_DA_DMIX (0xf) +#define RT5668_G_STO_DA_SFT 0 + +/* CBJ Control (0x000b) */ +#define RT5668_BST_CBJ_MASK (0xf << 8) +#define RT5668_BST_CBJ_SFT 8 + +/* Embeeded Jack and Type Detection Control 1 (0x0010) */ +#define RT5668_EMB_JD_EN (0x1 << 15) +#define RT5668_EMB_JD_EN_SFT 15 +#define RT5668_EMB_JD_RST (0x1 << 14) +#define RT5668_JD_MODE (0x1 << 13) +#define RT5668_JD_MODE_SFT 13 +#define RT5668_DET_TYPE (0x1 << 12) +#define RT5668_DET_TYPE_SFT 12 +#define RT5668_POLA_EXT_JD_MASK (0x1 << 11) +#define RT5668_POLA_EXT_JD_LOW (0x1 << 11) +#define RT5668_POLA_EXT_JD_HIGH (0x0 << 11) +#define RT5668_EXT_JD_DIG (0x1 << 9) +#define RT5668_POL_FAST_OFF_MASK (0x1 << 8) +#define RT5668_POL_FAST_OFF_HIGH (0x1 << 8) +#define RT5668_POL_FAST_OFF_LOW (0x0 << 8) +#define RT5668_FAST_OFF_MASK (0x1 << 7) +#define RT5668_FAST_OFF_EN (0x1 << 7) +#define RT5668_FAST_OFF_DIS (0x0 << 7) +#define RT5668_VREF_POW_MASK (0x1 << 6) +#define RT5668_VREF_POW_FSM (0x0 << 6) +#define RT5668_VREF_POW_REG (0x1 << 6) +#define RT5668_MB1_PATH_MASK (0x1 << 5) +#define RT5668_CTRL_MB1_REG (0x1 << 5) +#define RT5668_CTRL_MB1_FSM (0x0 << 5) +#define RT5668_MB2_PATH_MASK (0x1 << 4) +#define RT5668_CTRL_MB2_REG (0x1 << 4) +#define RT5668_CTRL_MB2_FSM (0x0 << 4) +#define RT5668_TRIG_JD_MASK (0x1 << 3) +#define RT5668_TRIG_JD_HIGH (0x1 << 3) +#define RT5668_TRIG_JD_LOW (0x0 << 3) +#define RT5668_MIC_CAP_MASK (0x1 << 1) +#define RT5668_MIC_CAP_HS (0x1 << 1) +#define RT5668_MIC_CAP_HP (0x0 << 1) +#define RT5668_MIC_CAP_SRC_MASK (0x1) +#define RT5668_MIC_CAP_SRC_REG (0x1) +#define RT5668_MIC_CAP_SRC_ANA (0x0) + +/* Embeeded Jack and Type Detection Control 2 (0x0011) */ +#define RT5668_EXT_JD_SRC (0x7 << 4) +#define RT5668_EXT_JD_SRC_SFT 4 +#define RT5668_EXT_JD_SRC_GPIO_JD1 (0x0 << 4) +#define RT5668_EXT_JD_SRC_GPIO_JD2 (0x1 << 4) +#define RT5668_EXT_JD_SRC_JDH (0x2 << 4) +#define RT5668_EXT_JD_SRC_JDL (0x3 << 4) +#define RT5668_EXT_JD_SRC_MANUAL (0x4 << 4) +#define RT5668_JACK_TYPE_MASK (0x3) + +/* Combo Jack and Type Detection Control 3 (0x0012) */ +#define RT5668_CBJ_IN_BUF_EN (0x1 << 7) + +/* Combo Jack and Type Detection Control 4 (0x0013) */ +#define RT5668_SEL_SHT_MID_TON_MASK (0x3 << 12) +#define RT5668_SEL_SHT_MID_TON_2 (0x0 << 12) +#define RT5668_SEL_SHT_MID_TON_3 (0x1 << 12) +#define RT5668_CBJ_JD_TEST_MASK (0x1 << 6) +#define RT5668_CBJ_JD_TEST_NORM (0x0 << 6) +#define RT5668_CBJ_JD_TEST_MODE (0x1 << 6) + +/* DAC1 Digital Volume (0x0019) */ +#define RT5668_DAC_L1_VOL_MASK (0xff << 8) +#define RT5668_DAC_L1_VOL_SFT 8 +#define RT5668_DAC_R1_VOL_MASK (0xff) +#define RT5668_DAC_R1_VOL_SFT 0 + +/* ADC Digital Volume Control (0x001c) */ +#define RT5668_ADC_L_VOL_MASK (0x7f << 8) +#define RT5668_ADC_L_VOL_SFT 8 +#define RT5668_ADC_R_VOL_MASK (0x7f) +#define RT5668_ADC_R_VOL_SFT 0 + +/* Stereo1 ADC Boost Gain Control (0x001f) */ +#define RT5668_STO1_ADC_L_BST_MASK (0x3 << 14) +#define RT5668_STO1_ADC_L_BST_SFT 14 +#define RT5668_STO1_ADC_R_BST_MASK (0x3 << 12) +#define RT5668_STO1_ADC_R_BST_SFT 12 + +/* Sidetone Control (0x0024) */ +#define RT5668_ST_SRC_SEL (0x1 << 8) +#define RT5668_ST_SRC_SFT 8 +#define RT5668_ST_EN_MASK (0x1 << 6) +#define RT5668_ST_DIS (0x0 << 6) +#define RT5668_ST_EN (0x1 << 6) +#define RT5668_ST_EN_SFT 6 + +/* Stereo1 ADC Mixer Control (0x0026) */ +#define RT5668_M_STO1_ADC_L1 (0x1 << 15) +#define RT5668_M_STO1_ADC_L1_SFT 15 +#define RT5668_M_STO1_ADC_L2 (0x1 << 14) +#define RT5668_M_STO1_ADC_L2_SFT 14 +#define RT5668_STO1_ADC1L_SRC_MASK (0x1 << 13) +#define RT5668_STO1_ADC1L_SRC_SFT 13 +#define RT5668_STO1_ADC1_SRC_ADC (0x1 << 13) +#define RT5668_STO1_ADC1_SRC_DACMIX (0x0 << 13) +#define RT5668_STO1_ADC2L_SRC_MASK (0x1 << 12) +#define RT5668_STO1_ADC2L_SRC_SFT 12 +#define RT5668_STO1_ADCL_SRC_MASK (0x3 << 10) +#define RT5668_STO1_ADCL_SRC_SFT 10 +#define RT5668_STO1_DD_L_SRC_MASK (0x1 << 9) +#define RT5668_STO1_DD_L_SRC_SFT 9 +#define RT5668_STO1_DMIC_SRC_MASK (0x1 << 8) +#define RT5668_STO1_DMIC_SRC_SFT 8 +#define RT5668_STO1_DMIC_SRC_DMIC2 (0x1 << 8) +#define RT5668_STO1_DMIC_SRC_DMIC1 (0x0 << 8) +#define RT5668_M_STO1_ADC_R1 (0x1 << 7) +#define RT5668_M_STO1_ADC_R1_SFT 7 +#define RT5668_M_STO1_ADC_R2 (0x1 << 6) +#define RT5668_M_STO1_ADC_R2_SFT 6 +#define RT5668_STO1_ADC1R_SRC_MASK (0x1 << 5) +#define RT5668_STO1_ADC1R_SRC_SFT 5 +#define RT5668_STO1_ADC2R_SRC_MASK (0x1 << 4) +#define RT5668_STO1_ADC2R_SRC_SFT 4 +#define RT5668_STO1_ADCR_SRC_MASK (0x3 << 2) +#define RT5668_STO1_ADCR_SRC_SFT 2 + +/* ADC Mixer to DAC Mixer Control (0x0029) */ +#define RT5668_M_ADCMIX_L (0x1 << 15) +#define RT5668_M_ADCMIX_L_SFT 15 +#define RT5668_M_DAC1_L (0x1 << 14) +#define RT5668_M_DAC1_L_SFT 14 +#define RT5668_DAC1_R_SEL_MASK (0x1 << 10) +#define RT5668_DAC1_R_SEL_SFT 10 +#define RT5668_DAC1_L_SEL_MASK (0x1 << 8) +#define RT5668_DAC1_L_SEL_SFT 8 +#define RT5668_M_ADCMIX_R (0x1 << 7) +#define RT5668_M_ADCMIX_R_SFT 7 +#define RT5668_M_DAC1_R (0x1 << 6) +#define RT5668_M_DAC1_R_SFT 6 + +/* Stereo1 DAC Mixer Control (0x002a) */ +#define RT5668_M_DAC_L1_STO_L (0x1 << 15) +#define RT5668_M_DAC_L1_STO_L_SFT 15 +#define RT5668_G_DAC_L1_STO_L_MASK (0x1 << 14) +#define RT5668_G_DAC_L1_STO_L_SFT 14 +#define RT5668_M_DAC_R1_STO_L (0x1 << 13) +#define RT5668_M_DAC_R1_STO_L_SFT 13 +#define RT5668_G_DAC_R1_STO_L_MASK (0x1 << 12) +#define RT5668_G_DAC_R1_STO_L_SFT 12 +#define RT5668_M_DAC_L1_STO_R (0x1 << 7) +#define RT5668_M_DAC_L1_STO_R_SFT 7 +#define RT5668_G_DAC_L1_STO_R_MASK (0x1 << 6) +#define RT5668_G_DAC_L1_STO_R_SFT 6 +#define RT5668_M_DAC_R1_STO_R (0x1 << 5) +#define RT5668_M_DAC_R1_STO_R_SFT 5 +#define RT5668_G_DAC_R1_STO_R_MASK (0x1 << 4) +#define RT5668_G_DAC_R1_STO_R_SFT 4 + +/* Analog DAC1 Input Source Control (0x002b) */ +#define RT5668_M_ST_STO_L (0x1 << 9) +#define RT5668_M_ST_STO_L_SFT 9 +#define RT5668_M_ST_STO_R (0x1 << 8) +#define RT5668_M_ST_STO_R_SFT 8 +#define RT5668_DAC_L1_SRC_MASK (0x3 << 4) +#define RT5668_A_DACL1_SFT 4 +#define RT5668_DAC_R1_SRC_MASK (0x3) +#define RT5668_A_DACR1_SFT 0 + +/* Digital Interface Data Control (0x0030) */ +#define RT5668_IF2_ADC_SEL_MASK (0x3 << 0) +#define RT5668_IF2_ADC_SEL_SFT 0 + +/* REC Left Mixer Control 2 (0x003c) */ +#define RT5668_G_CBJ_RM1_L (0x7 << 10) +#define RT5668_G_CBJ_RM1_L_SFT 10 +#define RT5668_M_CBJ_RM1_L (0x1 << 7) +#define RT5668_M_CBJ_RM1_L_SFT 7 + +/* Power Management for Digital 1 (0x0061) */ +#define RT5668_PWR_I2S1 (0x1 << 15) +#define RT5668_PWR_I2S1_BIT 15 +#define RT5668_PWR_I2S2 (0x1 << 14) +#define RT5668_PWR_I2S2_BIT 14 +#define RT5668_PWR_DAC_L1 (0x1 << 11) +#define RT5668_PWR_DAC_L1_BIT 11 +#define RT5668_PWR_DAC_R1 (0x1 << 10) +#define RT5668_PWR_DAC_R1_BIT 10 +#define RT5668_PWR_LDO (0x1 << 8) +#define RT5668_PWR_LDO_BIT 8 +#define RT5668_PWR_ADC_L1 (0x1 << 4) +#define RT5668_PWR_ADC_L1_BIT 4 +#define RT5668_PWR_ADC_R1 (0x1 << 3) +#define RT5668_PWR_ADC_R1_BIT 3 +#define RT5668_DIG_GATE_CTRL (0x1 << 0) +#define RT5668_DIG_GATE_CTRL_SFT 0 + + +/* Power Management for Digital 2 (0x0062) */ +#define RT5668_PWR_ADC_S1F (0x1 << 15) +#define RT5668_PWR_ADC_S1F_BIT 15 +#define RT5668_PWR_DAC_S1F (0x1 << 10) +#define RT5668_PWR_DAC_S1F_BIT 10 + +/* Power Management for Analog 1 (0x0063) */ +#define RT5668_PWR_VREF1 (0x1 << 15) +#define RT5668_PWR_VREF1_BIT 15 +#define RT5668_PWR_FV1 (0x1 << 14) +#define RT5668_PWR_FV1_BIT 14 +#define RT5668_PWR_VREF2 (0x1 << 13) +#define RT5668_PWR_VREF2_BIT 13 +#define RT5668_PWR_FV2 (0x1 << 12) +#define RT5668_PWR_FV2_BIT 12 +#define RT5668_LDO1_DBG_MASK (0x3 << 10) +#define RT5668_PWR_MB (0x1 << 9) +#define RT5668_PWR_MB_BIT 9 +#define RT5668_PWR_BG (0x1 << 7) +#define RT5668_PWR_BG_BIT 7 +#define RT5668_LDO1_BYPASS_MASK (0x1 << 6) +#define RT5668_LDO1_BYPASS (0x1 << 6) +#define RT5668_LDO1_NOT_BYPASS (0x0 << 6) +#define RT5668_PWR_MA_BIT 6 +#define RT5668_LDO1_DVO_MASK (0x3 << 4) +#define RT5668_LDO1_DVO_09 (0x0 << 4) +#define RT5668_LDO1_DVO_10 (0x1 << 4) +#define RT5668_LDO1_DVO_12 (0x2 << 4) +#define RT5668_LDO1_DVO_14 (0x3 << 4) +#define RT5668_HP_DRIVER_MASK (0x3 << 2) +#define RT5668_HP_DRIVER_1X (0x0 << 2) +#define RT5668_HP_DRIVER_3X (0x1 << 2) +#define RT5668_HP_DRIVER_5X (0x3 << 2) +#define RT5668_PWR_HA_L (0x1 << 1) +#define RT5668_PWR_HA_L_BIT 1 +#define RT5668_PWR_HA_R (0x1 << 0) +#define RT5668_PWR_HA_R_BIT 0 + +/* Power Management for Analog 2 (0x0064) */ +#define RT5668_PWR_MB1 (0x1 << 11) +#define RT5668_PWR_MB1_PWR_DOWN (0x0 << 11) +#define RT5668_PWR_MB1_BIT 11 +#define RT5668_PWR_MB2 (0x1 << 10) +#define RT5668_PWR_MB2_PWR_DOWN (0x0 << 10) +#define RT5668_PWR_MB2_BIT 10 +#define RT5668_PWR_JDH (0x1 << 3) +#define RT5668_PWR_JDH_BIT 3 +#define RT5668_PWR_JDL (0x1 << 2) +#define RT5668_PWR_JDL_BIT 2 +#define RT5668_PWR_RM1_L (0x1 << 1) +#define RT5668_PWR_RM1_L_BIT 1 + +/* Power Management for Analog 3 (0x0065) */ +#define RT5668_PWR_CBJ (0x1 << 9) +#define RT5668_PWR_CBJ_BIT 9 +#define RT5668_PWR_PLL (0x1 << 6) +#define RT5668_PWR_PLL_BIT 6 +#define RT5668_PWR_PLL2B (0x1 << 5) +#define RT5668_PWR_PLL2B_BIT 5 +#define RT5668_PWR_PLL2F (0x1 << 4) +#define RT5668_PWR_PLL2F_BIT 4 +#define RT5668_PWR_LDO2 (0x1 << 2) +#define RT5668_PWR_LDO2_BIT 2 +#define RT5668_PWR_DET_SPKVDD (0x1 << 1) +#define RT5668_PWR_DET_SPKVDD_BIT 1 + +/* Power Management for Mixer (0x0066) */ +#define RT5668_PWR_STO1_DAC_L (0x1 << 5) +#define RT5668_PWR_STO1_DAC_L_BIT 5 +#define RT5668_PWR_STO1_DAC_R (0x1 << 4) +#define RT5668_PWR_STO1_DAC_R_BIT 4 + +/* MCLK and System Clock Detection Control (0x006b) */ +#define RT5668_SYS_CLK_DET (0x1 << 15) +#define RT5668_SYS_CLK_DET_SFT 15 +#define RT5668_PLL1_CLK_DET (0x1 << 14) +#define RT5668_PLL1_CLK_DET_SFT 14 +#define RT5668_PLL2_CLK_DET (0x1 << 13) +#define RT5668_PLL2_CLK_DET_SFT 13 +#define RT5668_POW_CLK_DET2_SFT 8 +#define RT5668_POW_CLK_DET_SFT 0 + +/* Digital Microphone Control 1 (0x006e) */ +#define RT5668_DMIC_1_EN_MASK (0x1 << 15) +#define RT5668_DMIC_1_EN_SFT 15 +#define RT5668_DMIC_1_DIS (0x0 << 15) +#define RT5668_DMIC_1_EN (0x1 << 15) +#define RT5668_DMIC_1_DP_MASK (0x3 << 4) +#define RT5668_DMIC_1_DP_SFT 4 +#define RT5668_DMIC_1_DP_GPIO2 (0x0 << 4) +#define RT5668_DMIC_1_DP_GPIO5 (0x1 << 4) +#define RT5668_DMIC_CLK_MASK (0xf << 0) +#define RT5668_DMIC_CLK_SFT 0 + +/* I2S1 Audio Serial Data Port Control (0x0070) */ +#define RT5668_SEL_ADCDAT_MASK (0x1 << 15) +#define RT5668_SEL_ADCDAT_OUT (0x0 << 15) +#define RT5668_SEL_ADCDAT_IN (0x1 << 15) +#define RT5668_SEL_ADCDAT_SFT 15 +#define RT5668_I2S1_TX_CHL_MASK (0x7 << 12) +#define RT5668_I2S1_TX_CHL_SFT 12 +#define RT5668_I2S1_TX_CHL_16 (0x0 << 12) +#define RT5668_I2S1_TX_CHL_20 (0x1 << 12) +#define RT5668_I2S1_TX_CHL_24 (0x2 << 12) +#define RT5668_I2S1_TX_CHL_32 (0x3 << 12) +#define RT5668_I2S1_TX_CHL_8 (0x4 << 12) +#define RT5668_I2S1_RX_CHL_MASK (0x7 << 8) +#define RT5668_I2S1_RX_CHL_SFT 8 +#define RT5668_I2S1_RX_CHL_16 (0x0 << 8) +#define RT5668_I2S1_RX_CHL_20 (0x1 << 8) +#define RT5668_I2S1_RX_CHL_24 (0x2 << 8) +#define RT5668_I2S1_RX_CHL_32 (0x3 << 8) +#define RT5668_I2S1_RX_CHL_8 (0x4 << 8) +#define RT5668_I2S1_MONO_MASK (0x1 << 7) +#define RT5668_I2S1_MONO_EN (0x1 << 7) +#define RT5668_I2S1_MONO_DIS (0x0 << 7) +#define RT5668_I2S2_MONO_MASK (0x1 << 6) +#define RT5668_I2S2_MONO_EN (0x1 << 6) +#define RT5668_I2S2_MONO_DIS (0x0 << 6) +#define RT5668_I2S1_DL_MASK (0x7 << 4) +#define RT5668_I2S1_DL_SFT 4 +#define RT5668_I2S1_DL_16 (0x0 << 4) +#define RT5668_I2S1_DL_20 (0x1 << 4) +#define RT5668_I2S1_DL_24 (0x2 << 4) +#define RT5668_I2S1_DL_32 (0x3 << 4) +#define RT5668_I2S1_DL_8 (0x4 << 4) + +/* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */ +#define RT5668_I2S2_MS_MASK (0x1 << 15) +#define RT5668_I2S2_MS_SFT 15 +#define RT5668_I2S2_MS_M (0x0 << 15) +#define RT5668_I2S2_MS_S (0x1 << 15) +#define RT5668_I2S2_PIN_CFG_MASK (0x1 << 14) +#define RT5668_I2S2_PIN_CFG_SFT 14 +#define RT5668_I2S2_CLK_SEL_MASK (0x1 << 11) +#define RT5668_I2S2_CLK_SEL_SFT 11 +#define RT5668_I2S2_OUT_MASK (0x1 << 9) +#define RT5668_I2S2_OUT_SFT 9 +#define RT5668_I2S2_OUT_UM (0x0 << 9) +#define RT5668_I2S2_OUT_M (0x1 << 9) +#define RT5668_I2S_BP_MASK (0x1 << 8) +#define RT5668_I2S_BP_SFT 8 +#define RT5668_I2S_BP_NOR (0x0 << 8) +#define RT5668_I2S_BP_INV (0x1 << 8) +#define RT5668_I2S2_MONO_EN (0x1 << 6) +#define RT5668_I2S2_MONO_DIS (0x0 << 6) +#define RT5668_I2S2_DL_MASK (0x3 << 4) +#define RT5668_I2S2_DL_SFT 4 +#define RT5668_I2S2_DL_16 (0x0 << 4) +#define RT5668_I2S2_DL_20 (0x1 << 4) +#define RT5668_I2S2_DL_24 (0x2 << 4) +#define RT5668_I2S2_DL_8 (0x3 << 4) +#define RT5668_I2S_DF_MASK (0x7) +#define RT5668_I2S_DF_SFT 0 +#define RT5668_I2S_DF_I2S (0x0) +#define RT5668_I2S_DF_LEFT (0x1) +#define RT5668_I2S_DF_PCM_A (0x2) +#define RT5668_I2S_DF_PCM_B (0x3) +#define RT5668_I2S_DF_PCM_A_N (0x6) +#define RT5668_I2S_DF_PCM_B_N (0x7) + +/* ADC/DAC Clock Control 1 (0x0073) */ +#define RT5668_ADC_OSR_MASK (0xf << 12) +#define RT5668_ADC_OSR_SFT 12 +#define RT5668_ADC_OSR_D_1 (0x0 << 12) +#define RT5668_ADC_OSR_D_2 (0x1 << 12) +#define RT5668_ADC_OSR_D_4 (0x2 << 12) +#define RT5668_ADC_OSR_D_6 (0x3 << 12) +#define RT5668_ADC_OSR_D_8 (0x4 << 12) +#define RT5668_ADC_OSR_D_12 (0x5 << 12) +#define RT5668_ADC_OSR_D_16 (0x6 << 12) +#define RT5668_ADC_OSR_D_24 (0x7 << 12) +#define RT5668_ADC_OSR_D_32 (0x8 << 12) +#define RT5668_ADC_OSR_D_48 (0x9 << 12) +#define RT5668_I2S_M_DIV_MASK (0xf << 12) +#define RT5668_I2S_M_DIV_SFT 8 +#define RT5668_I2S_M_D_1 (0x0 << 8) +#define RT5668_I2S_M_D_2 (0x1 << 8) +#define RT5668_I2S_M_D_3 (0x2 << 8) +#define RT5668_I2S_M_D_4 (0x3 << 8) +#define RT5668_I2S_M_D_6 (0x4 << 8) +#define RT5668_I2S_M_D_8 (0x5 << 8) +#define RT5668_I2S_M_D_12 (0x6 << 8) +#define RT5668_I2S_M_D_16 (0x7 << 8) +#define RT5668_I2S_M_D_24 (0x8 << 8) +#define RT5668_I2S_M_D_32 (0x9 << 8) +#define RT5668_I2S_M_D_48 (0x10 << 8) +#define RT5668_I2S_CLK_SRC_MASK (0x7 << 4) +#define RT5668_I2S_CLK_SRC_SFT 4 +#define RT5668_I2S_CLK_SRC_MCLK (0x0 << 4) +#define RT5668_I2S_CLK_SRC_PLL1 (0x1 << 4) +#define RT5668_I2S_CLK_SRC_PLL2 (0x2 << 4) +#define RT5668_I2S_CLK_SRC_SDW (0x3 << 4) +#define RT5668_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */ +#define RT5668_DAC_OSR_MASK (0xf << 0) +#define RT5668_DAC_OSR_SFT 0 +#define RT5668_DAC_OSR_D_1 (0x0 << 0) +#define RT5668_DAC_OSR_D_2 (0x1 << 0) +#define RT5668_DAC_OSR_D_4 (0x2 << 0) +#define RT5668_DAC_OSR_D_6 (0x3 << 0) +#define RT5668_DAC_OSR_D_8 (0x4 << 0) +#define RT5668_DAC_OSR_D_12 (0x5 << 0) +#define RT5668_DAC_OSR_D_16 (0x6 << 0) +#define RT5668_DAC_OSR_D_24 (0x7 << 0) +#define RT5668_DAC_OSR_D_32 (0x8 << 0) +#define RT5668_DAC_OSR_D_48 (0x9 << 0) + +/* ADC/DAC Clock Control 2 (0x0074) */ +#define RT5668_I2S2_BCLK_MS2_MASK (0x1 << 11) +#define RT5668_I2S2_BCLK_MS2_SFT 11 +#define RT5668_I2S2_BCLK_MS2_32 (0x0 << 11) +#define RT5668_I2S2_BCLK_MS2_64 (0x1 << 11) + + +/* TDM control 1 (0x0079) */ +#define RT5668_TDM_TX_CH_MASK (0x3 << 12) +#define RT5668_TDM_TX_CH_2 (0x0 << 12) +#define RT5668_TDM_TX_CH_4 (0x1 << 12) +#define RT5668_TDM_TX_CH_6 (0x2 << 12) +#define RT5668_TDM_TX_CH_8 (0x3 << 12) +#define RT5668_TDM_RX_CH_MASK (0x3 << 8) +#define RT5668_TDM_RX_CH_2 (0x0 << 8) +#define RT5668_TDM_RX_CH_4 (0x1 << 8) +#define RT5668_TDM_RX_CH_6 (0x2 << 8) +#define RT5668_TDM_RX_CH_8 (0x3 << 8) +#define RT5668_TDM_ADC_LCA_MASK (0xf << 4) +#define RT5668_TDM_ADC_LCA_SFT 4 +#define RT5668_TDM_ADC_DL_SFT 0 + +/* TDM control 3 (0x007a) */ +#define RT5668_IF1_ADC1_SEL_SFT 14 +#define RT5668_IF1_ADC2_SEL_SFT 12 +#define RT5668_IF1_ADC3_SEL_SFT 10 +#define RT5668_IF1_ADC4_SEL_SFT 8 +#define RT5668_TDM_ADC_SEL_SFT 4 + +/* TDM/I2S control (0x007e) */ +#define RT5668_TDM_S_BP_MASK (0x1 << 15) +#define RT5668_TDM_S_BP_SFT 15 +#define RT5668_TDM_S_BP_NOR (0x0 << 15) +#define RT5668_TDM_S_BP_INV (0x1 << 15) +#define RT5668_TDM_S_LP_MASK (0x1 << 14) +#define RT5668_TDM_S_LP_SFT 14 +#define RT5668_TDM_S_LP_NOR (0x0 << 14) +#define RT5668_TDM_S_LP_INV (0x1 << 14) +#define RT5668_TDM_DF_MASK (0x7 << 11) +#define RT5668_TDM_DF_SFT 11 +#define RT5668_TDM_DF_I2S (0x0 << 11) +#define RT5668_TDM_DF_LEFT (0x1 << 11) +#define RT5668_TDM_DF_PCM_A (0x2 << 11) +#define RT5668_TDM_DF_PCM_B (0x3 << 11) +#define RT5668_TDM_DF_PCM_A_N (0x6 << 11) +#define RT5668_TDM_DF_PCM_B_N (0x7 << 11) +#define RT5668_TDM_CL_MASK (0x3 << 4) +#define RT5668_TDM_CL_16 (0x0 << 4) +#define RT5668_TDM_CL_20 (0x1 << 4) +#define RT5668_TDM_CL_24 (0x2 << 4) +#define RT5668_TDM_CL_32 (0x3 << 4) +#define RT5668_TDM_M_BP_MASK (0x1 << 2) +#define RT5668_TDM_M_BP_SFT 2 +#define RT5668_TDM_M_BP_NOR (0x0 << 2) +#define RT5668_TDM_M_BP_INV (0x1 << 2) +#define RT5668_TDM_M_LP_MASK (0x1 << 1) +#define RT5668_TDM_M_LP_SFT 1 +#define RT5668_TDM_M_LP_NOR (0x0 << 1) +#define RT5668_TDM_M_LP_INV (0x1 << 1) +#define RT5668_TDM_MS_MASK (0x1 << 0) +#define RT5668_TDM_MS_SFT 0 +#define RT5668_TDM_MS_M (0x0 << 0) +#define RT5668_TDM_MS_S (0x1 << 0) + +/* Global Clock Control (0x0080) */ +#define RT5668_SCLK_SRC_MASK (0x7 << 13) +#define RT5668_SCLK_SRC_SFT 13 +#define RT5668_SCLK_SRC_MCLK (0x0 << 13) +#define RT5668_SCLK_SRC_PLL1 (0x1 << 13) +#define RT5668_SCLK_SRC_PLL2 (0x2 << 13) +#define RT5668_SCLK_SRC_SDW (0x3 << 13) +#define RT5668_SCLK_SRC_RCCLK (0x4 << 13) +#define RT5668_PLL1_SRC_MASK (0x3 << 10) +#define RT5668_PLL1_SRC_SFT 10 +#define RT5668_PLL1_SRC_MCLK (0x0 << 10) +#define RT5668_PLL1_SRC_BCLK1 (0x1 << 10) +#define RT5668_PLL1_SRC_SDW (0x2 << 10) +#define RT5668_PLL1_SRC_RC (0x3 << 10) +#define RT5668_PLL2_SRC_MASK (0x3 << 8) +#define RT5668_PLL2_SRC_SFT 8 +#define RT5668_PLL2_SRC_MCLK (0x0 << 8) +#define RT5668_PLL2_SRC_BCLK1 (0x1 << 8) +#define RT5668_PLL2_SRC_SDW (0x2 << 8) +#define RT5668_PLL2_SRC_RC (0x3 << 8) + + + +#define RT5668_PLL_INP_MAX 40000000 +#define RT5668_PLL_INP_MIN 256000 +/* PLL M/N/K Code Control 1 (0x0081) */ +#define RT5668_PLL_N_MAX 0x001ff +#define RT5668_PLL_N_MASK (RT5668_PLL_N_MAX << 7) +#define RT5668_PLL_N_SFT 7 +#define RT5668_PLL_K_MAX 0x001f +#define RT5668_PLL_K_MASK (RT5668_PLL_K_MAX) +#define RT5668_PLL_K_SFT 0 + +/* PLL M/N/K Code Control 2 (0x0082) */ +#define RT5668_PLL_M_MAX 0x00f +#define RT5668_PLL_M_MASK (RT5668_PLL_M_MAX << 12) +#define RT5668_PLL_M_SFT 12 +#define RT5668_PLL_M_BP (0x1 << 11) +#define RT5668_PLL_M_BP_SFT 11 +#define RT5668_PLL_K_BP (0x1 << 10) +#define RT5668_PLL_K_BP_SFT 10 + +/* PLL tracking mode 1 (0x0083) */ +#define RT5668_DA_ASRC_MASK (0x1 << 13) +#define RT5668_DA_ASRC_SFT 13 +#define RT5668_DAC_STO1_ASRC_MASK (0x1 << 12) +#define RT5668_DAC_STO1_ASRC_SFT 12 +#define RT5668_AD_ASRC_MASK (0x1 << 8) +#define RT5668_AD_ASRC_SFT 8 +#define RT5668_AD_ASRC_SEL_MASK (0x1 << 4) +#define RT5668_AD_ASRC_SEL_SFT 4 +#define RT5668_DMIC_ASRC_MASK (0x1 << 3) +#define RT5668_DMIC_ASRC_SFT 3 +#define RT5668_ADC_STO1_ASRC_MASK (0x1 << 2) +#define RT5668_ADC_STO1_ASRC_SFT 2 +#define RT5668_DA_ASRC_SEL_MASK (0x1 << 0) +#define RT5668_DA_ASRC_SEL_SFT 0 + +/* PLL tracking mode 2 3 (0x0084)(0x0085)*/ +#define RT5668_FILTER_CLK_SEL_MASK (0x7 << 12) +#define RT5668_FILTER_CLK_SEL_SFT 12 + +/* ASRC Control 4 (0x0086) */ +#define RT5668_ASRCIN_FTK_N1_MASK (0x3 << 14) +#define RT5668_ASRCIN_FTK_N1_SFT 14 +#define RT5668_ASRCIN_FTK_N2_MASK (0x3 << 12) +#define RT5668_ASRCIN_FTK_N2_SFT 12 +#define RT5668_ASRCIN_FTK_M1_MASK (0x7 << 8) +#define RT5668_ASRCIN_FTK_M1_SFT 8 +#define RT5668_ASRCIN_FTK_M2_MASK (0x7 << 4) +#define RT5668_ASRCIN_FTK_M2_SFT 4 + +/* SoundWire reference clk (0x008d) */ +#define RT5668_PLL2_OUT_MASK (0x1 << 8) +#define RT5668_PLL2_OUT_98M (0x0 << 8) +#define RT5668_PLL2_OUT_49M (0x1 << 8) +#define RT5668_SDW_REF_2_MASK (0xf << 4) +#define RT5668_SDW_REF_2_SFT 4 +#define RT5668_SDW_REF_2_48K (0x0 << 4) +#define RT5668_SDW_REF_2_96K (0x1 << 4) +#define RT5668_SDW_REF_2_192K (0x2 << 4) +#define RT5668_SDW_REF_2_32K (0x3 << 4) +#define RT5668_SDW_REF_2_24K (0x4 << 4) +#define RT5668_SDW_REF_2_16K (0x5 << 4) +#define RT5668_SDW_REF_2_12K (0x6 << 4) +#define RT5668_SDW_REF_2_8K (0x7 << 4) +#define RT5668_SDW_REF_2_44K (0x8 << 4) +#define RT5668_SDW_REF_2_88K (0x9 << 4) +#define RT5668_SDW_REF_2_176K (0xa << 4) +#define RT5668_SDW_REF_2_353K (0xb << 4) +#define RT5668_SDW_REF_2_22K (0xc << 4) +#define RT5668_SDW_REF_2_384K (0xd << 4) +#define RT5668_SDW_REF_2_11K (0xe << 4) +#define RT5668_SDW_REF_1_MASK (0xf << 0) +#define RT5668_SDW_REF_1_SFT 0 +#define RT5668_SDW_REF_1_48K (0x0 << 0) +#define RT5668_SDW_REF_1_96K (0x1 << 0) +#define RT5668_SDW_REF_1_192K (0x2 << 0) +#define RT5668_SDW_REF_1_32K (0x3 << 0) +#define RT5668_SDW_REF_1_24K (0x4 << 0) +#define RT5668_SDW_REF_1_16K (0x5 << 0) +#define RT5668_SDW_REF_1_12K (0x6 << 0) +#define RT5668_SDW_REF_1_8K (0x7 << 0) +#define RT5668_SDW_REF_1_44K (0x8 << 0) +#define RT5668_SDW_REF_1_88K (0x9 << 0) +#define RT5668_SDW_REF_1_176K (0xa << 0) +#define RT5668_SDW_REF_1_353K (0xb << 0) +#define RT5668_SDW_REF_1_22K (0xc << 0) +#define RT5668_SDW_REF_1_384K (0xd << 0) +#define RT5668_SDW_REF_1_11K (0xe << 0) + +/* Depop Mode Control 1 (0x008e) */ +#define RT5668_PUMP_EN (0x1 << 3) +#define RT5668_PUMP_EN_SFT 3 +#define RT5668_CAPLESS_EN (0x1 << 0) +#define RT5668_CAPLESS_EN_SFT 0 + +/* Depop Mode Control 2 (0x8f) */ +#define RT5668_RAMP_MASK (0x1 << 12) +#define RT5668_RAMP_SFT 12 +#define RT5668_RAMP_DIS (0x0 << 12) +#define RT5668_RAMP_EN (0x1 << 12) +#define RT5668_BPS_MASK (0x1 << 11) +#define RT5668_BPS_SFT 11 +#define RT5668_BPS_DIS (0x0 << 11) +#define RT5668_BPS_EN (0x1 << 11) +#define RT5668_FAST_UPDN_MASK (0x1 << 10) +#define RT5668_FAST_UPDN_SFT 10 +#define RT5668_FAST_UPDN_DIS (0x0 << 10) +#define RT5668_FAST_UPDN_EN (0x1 << 10) +#define RT5668_VLO_MASK (0x1 << 7) +#define RT5668_VLO_SFT 7 +#define RT5668_VLO_3V (0x0 << 7) +#define RT5668_VLO_33V (0x1 << 7) + +/* HPOUT charge pump 1 (0x0091) */ +#define RT5668_OSW_L_MASK (0x1 << 11) +#define RT5668_OSW_L_SFT 11 +#define RT5668_OSW_L_DIS (0x0 << 11) +#define RT5668_OSW_L_EN (0x1 << 11) +#define RT5668_OSW_R_MASK (0x1 << 10) +#define RT5668_OSW_R_SFT 10 +#define RT5668_OSW_R_DIS (0x0 << 10) +#define RT5668_OSW_R_EN (0x1 << 10) +#define RT5668_PM_HP_MASK (0x3 << 8) +#define RT5668_PM_HP_SFT 8 +#define RT5668_PM_HP_LV (0x0 << 8) +#define RT5668_PM_HP_MV (0x1 << 8) +#define RT5668_PM_HP_HV (0x2 << 8) +#define RT5668_IB_HP_MASK (0x3 << 6) +#define RT5668_IB_HP_SFT 6 +#define RT5668_IB_HP_125IL (0x0 << 6) +#define RT5668_IB_HP_25IL (0x1 << 6) +#define RT5668_IB_HP_5IL (0x2 << 6) +#define RT5668_IB_HP_1IL (0x3 << 6) + +/* Micbias Control1 (0x93) */ +#define RT5668_MIC1_OV_MASK (0x3 << 14) +#define RT5668_MIC1_OV_SFT 14 +#define RT5668_MIC1_OV_2V7 (0x0 << 14) +#define RT5668_MIC1_OV_2V4 (0x1 << 14) +#define RT5668_MIC1_OV_2V25 (0x3 << 14) +#define RT5668_MIC1_OV_1V8 (0x4 << 14) +#define RT5668_MIC1_CLK_MASK (0x1 << 13) +#define RT5668_MIC1_CLK_SFT 13 +#define RT5668_MIC1_CLK_DIS (0x0 << 13) +#define RT5668_MIC1_CLK_EN (0x1 << 13) +#define RT5668_MIC1_OVCD_MASK (0x1 << 12) +#define RT5668_MIC1_OVCD_SFT 12 +#define RT5668_MIC1_OVCD_DIS (0x0 << 12) +#define RT5668_MIC1_OVCD_EN (0x1 << 12) +#define RT5668_MIC1_OVTH_MASK (0x3 << 10) +#define RT5668_MIC1_OVTH_SFT 10 +#define RT5668_MIC1_OVTH_768UA (0x0 << 10) +#define RT5668_MIC1_OVTH_960UA (0x1 << 10) +#define RT5668_MIC1_OVTH_1152UA (0x2 << 10) +#define RT5668_MIC1_OVTH_1960UA (0x3 << 10) +#define RT5668_MIC2_OV_MASK (0x3 << 8) +#define RT5668_MIC2_OV_SFT 8 +#define RT5668_MIC2_OV_2V7 (0x0 << 8) +#define RT5668_MIC2_OV_2V4 (0x1 << 8) +#define RT5668_MIC2_OV_2V25 (0x3 << 8) +#define RT5668_MIC2_OV_1V8 (0x4 << 8) +#define RT5668_MIC2_CLK_MASK (0x1 << 7) +#define RT5668_MIC2_CLK_SFT 7 +#define RT5668_MIC2_CLK_DIS (0x0 << 7) +#define RT5668_MIC2_CLK_EN (0x1 << 7) +#define RT5668_MIC2_OVTH_MASK (0x3 << 4) +#define RT5668_MIC2_OVTH_SFT 4 +#define RT5668_MIC2_OVTH_768UA (0x0 << 4) +#define RT5668_MIC2_OVTH_960UA (0x1 << 4) +#define RT5668_MIC2_OVTH_1152UA (0x2 << 4) +#define RT5668_MIC2_OVTH_1960UA (0x3 << 4) +#define RT5668_PWR_MB_MASK (0x1 << 3) +#define RT5668_PWR_MB_SFT 3 +#define RT5668_PWR_MB_PD (0x0 << 3) +#define RT5668_PWR_MB_PU (0x1 << 3) + +/* Micbias Control2 (0x0094) */ +#define RT5668_PWR_CLK25M_MASK (0x1 << 9) +#define RT5668_PWR_CLK25M_SFT 9 +#define RT5668_PWR_CLK25M_PD (0x0 << 9) +#define RT5668_PWR_CLK25M_PU (0x1 << 9) +#define RT5668_PWR_CLK1M_MASK (0x1 << 8) +#define RT5668_PWR_CLK1M_SFT 8 +#define RT5668_PWR_CLK1M_PD (0x0 << 8) +#define RT5668_PWR_CLK1M_PU (0x1 << 8) + +/* RC Clock Control (0x009f) */ +#define RT5668_POW_IRQ (0x1 << 15) +#define RT5668_POW_JDH (0x1 << 14) +#define RT5668_POW_JDL (0x1 << 13) +#define RT5668_POW_ANA (0x1 << 12) + +/* I2S Master Mode Clock Control 1 (0x00a0) */ +#define RT5668_CLK_SRC_MCLK (0x0) +#define RT5668_CLK_SRC_PLL1 (0x1) +#define RT5668_CLK_SRC_PLL2 (0x2) +#define RT5668_CLK_SRC_SDW (0x3) +#define RT5668_CLK_SRC_RCCLK (0x4) +#define RT5668_I2S_PD_1 (0x0) +#define RT5668_I2S_PD_2 (0x1) +#define RT5668_I2S_PD_3 (0x2) +#define RT5668_I2S_PD_4 (0x3) +#define RT5668_I2S_PD_6 (0x4) +#define RT5668_I2S_PD_8 (0x5) +#define RT5668_I2S_PD_12 (0x6) +#define RT5668_I2S_PD_16 (0x7) +#define RT5668_I2S_PD_24 (0x8) +#define RT5668_I2S_PD_32 (0x9) +#define RT5668_I2S_PD_48 (0xa) +#define RT5668_I2S2_SRC_MASK (0x3 << 4) +#define RT5668_I2S2_SRC_SFT 4 +#define RT5668_I2S2_M_PD_MASK (0xf << 0) +#define RT5668_I2S2_M_PD_SFT 0 + +/* IRQ Control 1 (0x00b6) */ +#define RT5668_JD1_PULSE_EN_MASK (0x1 << 10) +#define RT5668_JD1_PULSE_EN_SFT 10 +#define RT5668_JD1_PULSE_DIS (0x0 << 10) +#define RT5668_JD1_PULSE_EN (0x1 << 10) + +/* IRQ Control 2 (0x00b7) */ +#define RT5668_JD1_EN_MASK (0x1 << 15) +#define RT5668_JD1_EN_SFT 15 +#define RT5668_JD1_DIS (0x0 << 15) +#define RT5668_JD1_EN (0x1 << 15) +#define RT5668_JD1_POL_MASK (0x1 << 13) +#define RT5668_JD1_POL_NOR (0x0 << 13) +#define RT5668_JD1_POL_INV (0x1 << 13) + +/* IRQ Control 3 (0x00b8) */ +#define RT5668_IL_IRQ_MASK (0x1 << 7) +#define RT5668_IL_IRQ_DIS (0x0 << 7) +#define RT5668_IL_IRQ_EN (0x1 << 7) + +/* GPIO Control 1 (0x00c0) */ +#define RT5668_GP1_PIN_MASK (0x3 << 14) +#define RT5668_GP1_PIN_SFT 14 +#define RT5668_GP1_PIN_GPIO1 (0x0 << 14) +#define RT5668_GP1_PIN_IRQ (0x1 << 14) +#define RT5668_GP1_PIN_DMIC_CLK (0x2 << 14) +#define RT5668_GP2_PIN_MASK (0x3 << 12) +#define RT5668_GP2_PIN_SFT 12 +#define RT5668_GP2_PIN_GPIO2 (0x0 << 12) +#define RT5668_GP2_PIN_LRCK2 (0x1 << 12) +#define RT5668_GP2_PIN_DMIC_SDA (0x2 << 12) +#define RT5668_GP3_PIN_MASK (0x3 << 10) +#define RT5668_GP3_PIN_SFT 10 +#define RT5668_GP3_PIN_GPIO3 (0x0 << 10) +#define RT5668_GP3_PIN_BCLK2 (0x1 << 10) +#define RT5668_GP3_PIN_DMIC_CLK (0x2 << 10) +#define RT5668_GP4_PIN_MASK (0x3 << 8) +#define RT5668_GP4_PIN_SFT 8 +#define RT5668_GP4_PIN_GPIO4 (0x0 << 8) +#define RT5668_GP4_PIN_ADCDAT1 (0x1 << 8) +#define RT5668_GP4_PIN_DMIC_CLK (0x2 << 8) +#define RT5668_GP4_PIN_ADCDAT2 (0x3 << 8) +#define RT5668_GP5_PIN_MASK (0x3 << 6) +#define RT5668_GP5_PIN_SFT 6 +#define RT5668_GP5_PIN_GPIO5 (0x0 << 6) +#define RT5668_GP5_PIN_DACDAT1 (0x1 << 6) +#define RT5668_GP5_PIN_DMIC_SDA (0x2 << 6) +#define RT5668_GP6_PIN_MASK (0x1 << 5) +#define RT5668_GP6_PIN_SFT 5 +#define RT5668_GP6_PIN_GPIO6 (0x0 << 5) +#define RT5668_GP6_PIN_LRCK1 (0x1 << 5) + +/* GPIO Control 2 (0x00c1)*/ +#define RT5668_GP1_PF_MASK (0x1 << 15) +#define RT5668_GP1_PF_IN (0x0 << 15) +#define RT5668_GP1_PF_OUT (0x1 << 15) +#define RT5668_GP1_OUT_MASK (0x1 << 14) +#define RT5668_GP1_OUT_L (0x0 << 14) +#define RT5668_GP1_OUT_H (0x1 << 14) +#define RT5668_GP2_PF_MASK (0x1 << 13) +#define RT5668_GP2_PF_IN (0x0 << 13) +#define RT5668_GP2_PF_OUT (0x1 << 13) +#define RT5668_GP2_OUT_MASK (0x1 << 12) +#define RT5668_GP2_OUT_L (0x0 << 12) +#define RT5668_GP2_OUT_H (0x1 << 12) +#define RT5668_GP3_PF_MASK (0x1 << 11) +#define RT5668_GP3_PF_IN (0x0 << 11) +#define RT5668_GP3_PF_OUT (0x1 << 11) +#define RT5668_GP3_OUT_MASK (0x1 << 10) +#define RT5668_GP3_OUT_L (0x0 << 10) +#define RT5668_GP3_OUT_H (0x1 << 10) +#define RT5668_GP4_PF_MASK (0x1 << 9) +#define RT5668_GP4_PF_IN (0x0 << 9) +#define RT5668_GP4_PF_OUT (0x1 << 9) +#define RT5668_GP4_OUT_MASK (0x1 << 8) +#define RT5668_GP4_OUT_L (0x0 << 8) +#define RT5668_GP4_OUT_H (0x1 << 8) +#define RT5668_GP5_PF_MASK (0x1 << 7) +#define RT5668_GP5_PF_IN (0x0 << 7) +#define RT5668_GP5_PF_OUT (0x1 << 7) +#define RT5668_GP5_OUT_MASK (0x1 << 6) +#define RT5668_GP5_OUT_L (0x0 << 6) +#define RT5668_GP5_OUT_H (0x1 << 6) +#define RT5668_GP6_PF_MASK (0x1 << 5) +#define RT5668_GP6_PF_IN (0x0 << 5) +#define RT5668_GP6_PF_OUT (0x1 << 5) +#define RT5668_GP6_OUT_MASK (0x1 << 4) +#define RT5668_GP6_OUT_L (0x0 << 4) +#define RT5668_GP6_OUT_H (0x1 << 4) + + +/* GPIO Status (0x00c2) */ +#define RT5668_GP6_STA (0x1 << 6) +#define RT5668_GP5_STA (0x1 << 5) +#define RT5668_GP4_STA (0x1 << 4) +#define RT5668_GP3_STA (0x1 << 3) +#define RT5668_GP2_STA (0x1 << 2) +#define RT5668_GP1_STA (0x1 << 1) + +/* Soft volume and zero cross control 1 (0x00d9) */ +#define RT5668_SV_MASK (0x1 << 15) +#define RT5668_SV_SFT 15 +#define RT5668_SV_DIS (0x0 << 15) +#define RT5668_SV_EN (0x1 << 15) +#define RT5668_ZCD_MASK (0x1 << 10) +#define RT5668_ZCD_SFT 10 +#define RT5668_ZCD_PD (0x0 << 10) +#define RT5668_ZCD_PU (0x1 << 10) +#define RT5668_SV_DLY_MASK (0xf) +#define RT5668_SV_DLY_SFT 0 + +/* Soft volume and zero cross control 2 (0x00da) */ +#define RT5668_ZCD_BST1_CBJ_MASK (0x1 << 7) +#define RT5668_ZCD_BST1_CBJ_SFT 7 +#define RT5668_ZCD_BST1_CBJ_DIS (0x0 << 7) +#define RT5668_ZCD_BST1_CBJ_EN (0x1 << 7) +#define RT5668_ZCD_RECMIX_MASK (0x1) +#define RT5668_ZCD_RECMIX_SFT 0 +#define RT5668_ZCD_RECMIX_DIS (0x0) +#define RT5668_ZCD_RECMIX_EN (0x1) + +/* 4 Button Inline Command Control 2 (0x00e3) */ +#define RT5668_4BTN_IL_MASK (0x1 << 15) +#define RT5668_4BTN_IL_EN (0x1 << 15) +#define RT5668_4BTN_IL_DIS (0x0 << 15) +#define RT5668_4BTN_IL_RST_MASK (0x1 << 14) +#define RT5668_4BTN_IL_NOR (0x1 << 14) +#define RT5668_4BTN_IL_RST (0x0 << 14) + +/* Analog JD Control (0x00f0) */ +#define RT5668_JDH_RS_MASK (0x1 << 4) +#define RT5668_JDH_NO_PLUG (0x1 << 4) +#define RT5668_JDH_PLUG (0x0 << 4) + +/* Chopper and Clock control for DAC (0x013a)*/ +#define RT5668_CKXEN_DAC1_MASK (0x1 << 13) +#define RT5668_CKXEN_DAC1_SFT 13 +#define RT5668_CKGEN_DAC1_MASK (0x1 << 12) +#define RT5668_CKGEN_DAC1_SFT 12 + +/* Chopper and Clock control for ADC (0x013b)*/ +#define RT5668_CKXEN_ADC1_MASK (0x1 << 13) +#define RT5668_CKXEN_ADC1_SFT 13 +#define RT5668_CKGEN_ADC1_MASK (0x1 << 12) +#define RT5668_CKGEN_ADC1_SFT 12 + +/* Volume test (0x013f)*/ +#define RT5668_SEL_CLK_VOL_MASK (0x1 << 15) +#define RT5668_SEL_CLK_VOL_EN (0x1 << 15) +#define RT5668_SEL_CLK_VOL_DIS (0x0 << 15) + +/* Test Mode Control 1 (0x0145) */ +#define RT5668_AD2DA_LB_MASK (0x1 << 10) +#define RT5668_AD2DA_LB_SFT 10 + +/* Stereo Noise Gate Control 1 (0x0160) */ +#define RT5668_NG2_EN_MASK (0x1 << 15) +#define RT5668_NG2_EN (0x1 << 15) +#define RT5668_NG2_DIS (0x0 << 15) + +/* Stereo1 DAC Silence Detection Control (0x0190) */ +#define RT5668_DEB_STO_DAC_MASK (0x7 << 4) +#define RT5668_DEB_80_MS (0x0 << 4) + +/* SAR ADC Inline Command Control 1 (0x0210) */ +#define RT5668_SAR_BUTT_DET_MASK (0x1 << 15) +#define RT5668_SAR_BUTT_DET_EN (0x1 << 15) +#define RT5668_SAR_BUTT_DET_DIS (0x0 << 15) +#define RT5668_SAR_BUTDET_MODE_MASK (0x1 << 14) +#define RT5668_SAR_BUTDET_POW_SAV (0x1 << 14) +#define RT5668_SAR_BUTDET_POW_NORM (0x0 << 14) +#define RT5668_SAR_BUTDET_RST_MASK (0x1 << 13) +#define RT5668_SAR_BUTDET_RST_NORMAL (0x1 << 13) +#define RT5668_SAR_BUTDET_RST (0x0 << 13) +#define RT5668_SAR_POW_MASK (0x1 << 12) +#define RT5668_SAR_POW_EN (0x1 << 12) +#define RT5668_SAR_POW_DIS (0x0 << 12) +#define RT5668_SAR_RST_MASK (0x1 << 11) +#define RT5668_SAR_RST_NORMAL (0x1 << 11) +#define RT5668_SAR_RST (0x0 << 11) +#define RT5668_SAR_BYPASS_MASK (0x1 << 10) +#define RT5668_SAR_BYPASS_EN (0x1 << 10) +#define RT5668_SAR_BYPASS_DIS (0x0 << 10) +#define RT5668_SAR_SEL_MB1_MASK (0x1 << 9) +#define RT5668_SAR_SEL_MB1_SEL (0x1 << 9) +#define RT5668_SAR_SEL_MB1_NOSEL (0x0 << 9) +#define RT5668_SAR_SEL_MB2_MASK (0x1 << 8) +#define RT5668_SAR_SEL_MB2_SEL (0x1 << 8) +#define RT5668_SAR_SEL_MB2_NOSEL (0x0 << 8) +#define RT5668_SAR_SEL_MODE_MASK (0x1 << 7) +#define RT5668_SAR_SEL_MODE_CMP (0x1 << 7) +#define RT5668_SAR_SEL_MODE_ADC (0x0 << 7) +#define RT5668_SAR_SEL_MB1_MB2_MASK (0x1 << 5) +#define RT5668_SAR_SEL_MB1_MB2_AUTO (0x1 << 5) +#define RT5668_SAR_SEL_MB1_MB2_MANU (0x0 << 5) +#define RT5668_SAR_SEL_SIGNAL_MASK (0x1 << 4) +#define RT5668_SAR_SEL_SIGNAL_AUTO (0x1 << 4) +#define RT5668_SAR_SEL_SIGNAL_MANU (0x0 << 4) + +/* SAR ADC Inline Command Control 13 (0x021c) */ +#define RT5668_SAR_SOUR_MASK (0x3f) +#define RT5668_SAR_SOUR_BTN (0x3f) +#define RT5668_SAR_SOUR_TYPE (0x0) + + +/* System Clock Source */ +enum { + RT5668_SCLK_S_MCLK, + RT5668_SCLK_S_PLL1, + RT5668_SCLK_S_PLL2, + RT5668_SCLK_S_RCCLK, +}; + +/* PLL Source */ +enum { + RT5668_PLL1_S_MCLK, + RT5668_PLL1_S_BCLK1, + RT5668_PLL1_S_RCCLK, +}; + +enum { + RT5668_AIF1, + RT5668_AIF2, + RT5668_AIFS +}; + +/* filter mask */ +enum { + RT5668_DA_STEREO1_FILTER = 0x1, + RT5668_AD_STEREO1_FILTER = (0x1 << 1), +}; + +enum { + RT5668_CLK_SEL_SYS, + RT5668_CLK_SEL_I2S1_ASRC, + RT5668_CLK_SEL_I2S2_ASRC, +}; + +int rt5668_sel_asrc_clk_src(struct snd_soc_component *component, + unsigned int filter_mask, unsigned int clk_src); + +#endif /* __RT5668_H__ */ diff --git a/sound/soc/codecs/rt5670.c b/sound/soc/codecs/rt5670.c index dc7df337d5f8..732ef928b25d 100644 --- a/sound/soc/codecs/rt5670.c +++ b/sound/soc/codecs/rt5670.c @@ -71,7 +71,7 @@ static const struct regmap_range_cfg rt5670_ranges[] = { static const struct reg_sequence init_list[] = { { RT5670_PR_BASE + 0x14, 0x9a8a }, - { RT5670_PR_BASE + 0x38, 0x3ba1 }, + { RT5670_PR_BASE + 0x38, 0x1fe1 }, { RT5670_PR_BASE + 0x3d, 0x3640 }, { 0x8a, 0x0123 }, }; diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index bc1a23dd7c2d..8a0181a2db08 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -5006,13 +5006,6 @@ static const struct regmap_config rt5677_regmap = { .num_ranges = ARRAY_SIZE(rt5677_ranges), }; -static const struct i2c_device_id rt5677_i2c_id[] = { - { "rt5677", RT5677 }, - { "rt5676", RT5676 }, - { } -}; -MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id); - static const struct of_device_id rt5677_of_match[] = { { .compatible = "realtek,rt5677", RT5677 }, { } @@ -5130,8 +5123,7 @@ static void rt5677_free_irq(struct i2c_client *i2c) regmap_del_irq_chip(i2c->irq, rt5677->irq_data); } -static int rt5677_i2c_probe(struct i2c_client *i2c, - const struct i2c_device_id *id) +static int rt5677_i2c_probe(struct i2c_client *i2c) { struct rt5677_priv *rt5677; int ret; @@ -5278,9 +5270,8 @@ static struct i2c_driver rt5677_i2c_driver = { .of_match_table = rt5677_of_match, .acpi_match_table = ACPI_PTR(rt5677_acpi_match), }, - .probe = rt5677_i2c_probe, + .probe_new = rt5677_i2c_probe, .remove = rt5677_i2c_remove, - .id_table = rt5677_i2c_id, }; module_i2c_driver(rt5677_i2c_driver); diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c index 7c1d65830c05..60764f6201b1 100644 --- a/sound/soc/codecs/sgtl5000.c +++ b/sound/soc/codecs/sgtl5000.c @@ -1,12 +1,8 @@ -/* - * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver - * - * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// sgtl5000.c -- SGTL5000 ALSA SoC Audio driver +// +// Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. #include <linux/module.h> #include <linux/moduleparam.h> @@ -457,7 +453,7 @@ static int dac_put_volsw(struct snd_kcontrol *kcontrol, * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==> * dB = ( fls(register_value) - 14.347 ) * 6.02 * - * As this calculation is expensive and the threshold dB values may not exeed + * As this calculation is expensive and the threshold dB values may not exceed * 0 to 96 we use pre-calculated values. */ static int avc_get_threshold(struct snd_kcontrol *kcontrol, @@ -490,7 +486,7 @@ static int avc_get_threshold(struct snd_kcontrol *kcontrol, * * The register value is calculated by following formula: * register_value = 10^(dB/20) * 0.636 * 2^15 - * As this calculation is expensive and the threshold dB values may not exeed + * As this calculation is expensive and the threshold dB values may not exceed * 0 to 96 we use pre-calculated values. */ static int avc_put_threshold(struct snd_kcontrol *kcontrol, diff --git a/sound/soc/codecs/sgtl5000.h b/sound/soc/codecs/sgtl5000.h index 28cf637155bb..18cae08bbd3a 100644 --- a/sound/soc/codecs/sgtl5000.h +++ b/sound/soc/codecs/sgtl5000.h @@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * sgtl5000.h - SGTL5000 audio codec interface * * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _SGTL5000_H diff --git a/sound/soc/codecs/ssm2305.c b/sound/soc/codecs/ssm2305.c new file mode 100644 index 000000000000..2968959c4b75 --- /dev/null +++ b/sound/soc/codecs/ssm2305.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Analog Devices SSM2305 Amplifier Driver +// +// Copyright (C) 2018 Pengutronix, Marco Felsch <kernel@pengutronix.de> +// + +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <sound/soc.h> + +#define DRV_NAME "ssm2305" + +struct ssm2305 { + /* shutdown gpio */ + struct gpio_desc *gpiod_shutdown; +}; + +static int ssm2305_power_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kctrl, int event) +{ + struct snd_soc_component *c = snd_soc_dapm_to_component(w->dapm); + struct ssm2305 *data = snd_soc_component_get_drvdata(c); + + gpiod_set_value_cansleep(data->gpiod_shutdown, + SND_SOC_DAPM_EVENT_ON(event)); + + return 0; +} + +static const struct snd_soc_dapm_widget ssm2305_dapm_widgets[] = { + /* Stereo input/output */ + SND_SOC_DAPM_INPUT("L_IN"), + SND_SOC_DAPM_INPUT("R_IN"), + SND_SOC_DAPM_OUTPUT("L_OUT"), + SND_SOC_DAPM_OUTPUT("R_OUT"), + + SND_SOC_DAPM_SUPPLY("Power", SND_SOC_NOPM, 0, 0, ssm2305_power_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), +}; + +static const struct snd_soc_dapm_route ssm2305_dapm_routes[] = { + { "L_OUT", NULL, "L_IN" }, + { "R_OUT", NULL, "R_IN" }, + { "L_IN", NULL, "Power" }, + { "R_IN", NULL, "Power" }, +}; + +static const struct snd_soc_component_driver ssm2305_component_driver = { + .dapm_widgets = ssm2305_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(ssm2305_dapm_widgets), + .dapm_routes = ssm2305_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(ssm2305_dapm_routes), +}; + +static int ssm2305_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ssm2305 *priv; + int err; + + /* Allocate the private data */ + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + + /* Get shutdown gpio */ + priv->gpiod_shutdown = devm_gpiod_get(dev, "shutdown", + GPIOD_OUT_LOW); + if (IS_ERR(priv->gpiod_shutdown)) { + err = PTR_ERR(priv->gpiod_shutdown); + if (err != -EPROBE_DEFER) + dev_err(dev, "Failed to get 'shutdown' gpio: %d\n", + err); + return err; + } + + return devm_snd_soc_register_component(dev, &ssm2305_component_driver, + NULL, 0); +} + +#ifdef CONFIG_OF +static const struct of_device_id ssm2305_of_match[] = { + { .compatible = "adi,ssm2305", }, + { } +}; +MODULE_DEVICE_TABLE(of, ssm2305_of_match); +#endif + +static struct platform_driver ssm2305_driver = { + .driver = { + .name = DRV_NAME, + .of_match_table = of_match_ptr(ssm2305_of_match), + }, + .probe = ssm2305_probe, +}; + +module_platform_driver(ssm2305_driver); + +MODULE_DESCRIPTION("ASoC SSM2305 amplifier driver"); +MODULE_AUTHOR("Marco Felsch <m.felsch@pengutronix.de>"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/tas6424.c b/sound/soc/codecs/tas6424.c index 4f3a16c520a2..14999b999fd3 100644 --- a/sound/soc/codecs/tas6424.c +++ b/sound/soc/codecs/tas6424.c @@ -16,6 +16,7 @@ #include <linux/slab.h> #include <linux/regulator/consumer.h> #include <linux/delay.h> +#include <linux/gpio/consumer.h> #include <sound/pcm.h> #include <sound/pcm_params.h> @@ -43,6 +44,8 @@ struct tas6424_data { unsigned int last_fault1; unsigned int last_fault2; unsigned int last_warn; + struct gpio_desc *standby_gpio; + struct gpio_desc *mute_gpio; }; /* @@ -61,6 +64,8 @@ static const struct snd_kcontrol_new tas6424_snd_controls[] = { TAS6424_CH3_VOL_CTRL, 0, 0xff, 0, dac_tlv), SOC_SINGLE_TLV("Speaker Driver CH4 Playback Volume", TAS6424_CH4_VOL_CTRL, 0, 0xff, 0, dac_tlv), + SOC_SINGLE_STROBE("Auto Diagnostics Switch", TAS6424_DC_DIAG_CTRL1, + TAS6424_LDGBYPASS_SHIFT, 1), }; static int tas6424_dac_event(struct snd_soc_dapm_widget *w, @@ -249,10 +254,16 @@ static int tas6424_set_dai_tdm_slot(struct snd_soc_dai *dai, static int tas6424_mute(struct snd_soc_dai *dai, int mute) { struct snd_soc_component *component = dai->component; + struct tas6424_data *tas6424 = snd_soc_component_get_drvdata(component); unsigned int val; dev_dbg(component->dev, "%s() mute=%d\n", __func__, mute); + if (tas6424->mute_gpio) { + gpiod_set_value_cansleep(tas6424->mute_gpio, mute); + return 0; + } + if (mute) val = TAS6424_ALL_STATE_MUTE; else @@ -287,6 +298,12 @@ static int tas6424_power_on(struct snd_soc_component *component) { struct tas6424_data *tas6424 = snd_soc_component_get_drvdata(component); int ret; + u8 chan_states; + int no_auto_diags = 0; + unsigned int reg_val; + + if (!regmap_read(tas6424->regmap, TAS6424_DC_DIAG_CTRL1, ®_val)) + no_auto_diags = reg_val & TAS6424_LDGBYPASS_MASK; ret = regulator_bulk_enable(ARRAY_SIZE(tas6424->supplies), tas6424->supplies); @@ -303,12 +320,25 @@ static int tas6424_power_on(struct snd_soc_component *component) return ret; } - snd_soc_component_write(component, TAS6424_CH_STATE_CTRL, TAS6424_ALL_STATE_MUTE); + if (tas6424->mute_gpio) { + gpiod_set_value_cansleep(tas6424->mute_gpio, 0); + /* + * channels are muted via the mute pin. Don't also mute + * them via the registers so that subsequent register + * access is not necessary to un-mute the channels + */ + chan_states = TAS6424_ALL_STATE_PLAY; + } else { + chan_states = TAS6424_ALL_STATE_MUTE; + } + snd_soc_component_write(component, TAS6424_CH_STATE_CTRL, chan_states); /* any time we come out of HIZ, the output channels automatically run DC - * load diagnostics, wait here until this completes + * load diagnostics if autodiagnotics are enabled. wait here until this + * completes. */ - msleep(230); + if (!no_auto_diags) + msleep(230); return 0; } @@ -627,6 +657,38 @@ static int tas6424_i2c_probe(struct i2c_client *client, return ret; } + /* + * Get control of the standby pin and set it LOW to take the codec + * out of the stand-by mode. + * Note: The actual pin polarity is taken care of in the GPIO lib + * according the polarity specified in the DTS. + */ + tas6424->standby_gpio = devm_gpiod_get_optional(dev, "standby", + GPIOD_OUT_LOW); + if (IS_ERR(tas6424->standby_gpio)) { + if (PTR_ERR(tas6424->standby_gpio) == -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_info(dev, "failed to get standby GPIO: %ld\n", + PTR_ERR(tas6424->standby_gpio)); + tas6424->standby_gpio = NULL; + } + + /* + * Get control of the mute pin and set it HIGH in order to start with + * all the output muted. + * Note: The actual pin polarity is taken care of in the GPIO lib + * according the polarity specified in the DTS. + */ + tas6424->mute_gpio = devm_gpiod_get_optional(dev, "mute", + GPIOD_OUT_HIGH); + if (IS_ERR(tas6424->mute_gpio)) { + if (PTR_ERR(tas6424->mute_gpio) == -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_info(dev, "failed to get nmute GPIO: %ld\n", + PTR_ERR(tas6424->mute_gpio)); + tas6424->mute_gpio = NULL; + } + for (i = 0; i < ARRAY_SIZE(tas6424->supplies); i++) tas6424->supplies[i].supply = tas6424_supply_names[i]; ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(tas6424->supplies), @@ -671,6 +733,10 @@ static int tas6424_i2c_remove(struct i2c_client *client) cancel_delayed_work_sync(&tas6424->fault_check_work); + /* put the codec in stand-by */ + if (tas6424->standby_gpio) + gpiod_set_value_cansleep(tas6424->standby_gpio, 1); + ret = regulator_bulk_disable(ARRAY_SIZE(tas6424->supplies), tas6424->supplies); if (ret < 0) { diff --git a/sound/soc/codecs/tas6424.h b/sound/soc/codecs/tas6424.h index 430588328a06..b5958c45ed0e 100644 --- a/sound/soc/codecs/tas6424.h +++ b/sound/soc/codecs/tas6424.h @@ -111,6 +111,10 @@ TAS6424_CH3_STATE_DIAG | \ TAS6424_CH4_STATE_DIAG) +/* TAS6424_DC_DIAG_CTRL1 */ +#define TAS6424_LDGBYPASS_SHIFT 0 +#define TAS6424_LDGBYPASS_MASK BIT(TAS6424_LDGBYPASS_SHIFT) + /* TAS6424_GLOB_FAULT1_REG */ #define TAS6424_FAULT_CLOCK BIT(4) #define TAS6424_FAULT_PVDD_OV BIT(3) diff --git a/sound/soc/codecs/tfa9879.c b/sound/soc/codecs/tfa9879.c index 6d213c6d3920..abc114a3ae2b 100644 --- a/sound/soc/codecs/tfa9879.c +++ b/sound/soc/codecs/tfa9879.c @@ -1,15 +1,9 @@ -/* - * tfa9879.c -- driver for NXP Semiconductors TFA9879 - * - * Copyright (C) 2014 Axentia Technologies AB - * Author: Peter Rosin <peda@axentia.se> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// tfa9879.c -- driver for NXP Semiconductors TFA9879 +// +// Copyright (C) 2014 Axentia Technologies AB +// Author: Peter Rosin <peda@axentia.se> #include <linux/module.h> #include <linux/init.h> @@ -88,13 +82,14 @@ static int tfa9879_hw_params(struct snd_pcm_substream *substream, } if (tfa9879->lsb_justified) - snd_soc_component_update_bits(component, TFA9879_SERIAL_INTERFACE_1, - TFA9879_I2S_SET_MASK, - i2s_set << TFA9879_I2S_SET_SHIFT); + snd_soc_component_update_bits(component, + TFA9879_SERIAL_INTERFACE_1, + TFA9879_I2S_SET_MASK, + i2s_set << TFA9879_I2S_SET_SHIFT); snd_soc_component_update_bits(component, TFA9879_SERIAL_INTERFACE_1, - TFA9879_I2S_FS_MASK, - fs << TFA9879_I2S_FS_SHIFT); + TFA9879_I2S_FS_MASK, + fs << TFA9879_I2S_FS_SHIFT); return 0; } @@ -103,8 +98,8 @@ static int tfa9879_digital_mute(struct snd_soc_dai *dai, int mute) struct snd_soc_component *component = dai->component; snd_soc_component_update_bits(component, TFA9879_MISC_CONTROL, - TFA9879_S_MUTE_MASK, - !!mute << TFA9879_S_MUTE_SHIFT); + TFA9879_S_MUTE_MASK, + !!mute << TFA9879_S_MUTE_SHIFT); return 0; } @@ -152,11 +147,11 @@ static int tfa9879_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) } snd_soc_component_update_bits(component, TFA9879_SERIAL_INTERFACE_1, - TFA9879_SCK_POL_MASK, - sck_pol << TFA9879_SCK_POL_SHIFT); + TFA9879_SCK_POL_MASK, + sck_pol << TFA9879_SCK_POL_SHIFT); snd_soc_component_update_bits(component, TFA9879_SERIAL_INTERFACE_1, - TFA9879_I2S_SET_MASK, - i2s_set << TFA9879_I2S_SET_SHIFT); + TFA9879_I2S_SET_MASK, + i2s_set << TFA9879_I2S_SET_SHIFT); return 0; } @@ -276,8 +271,7 @@ static struct snd_soc_dai_driver tfa9879_dai = { .ops = &tfa9879_dai_ops, }; -static int tfa9879_i2c_probe(struct i2c_client *i2c, - const struct i2c_device_id *id) +static int tfa9879_i2c_probe(struct i2c_client *i2c) { struct tfa9879_priv *tfa9879; int i; @@ -298,7 +292,7 @@ static int tfa9879_i2c_probe(struct i2c_client *i2c, tfa9879_regs[i].reg, tfa9879_regs[i].def); return devm_snd_soc_register_component(&i2c->dev, &tfa9879_component, - &tfa9879_dai, 1); + &tfa9879_dai, 1); } static const struct i2c_device_id tfa9879_i2c_id[] = { @@ -318,7 +312,7 @@ static struct i2c_driver tfa9879_i2c_driver = { .name = "tfa9879", .of_match_table = tfa9879_of_match, }, - .probe = tfa9879_i2c_probe, + .probe_new = tfa9879_i2c_probe, .id_table = tfa9879_i2c_id, }; diff --git a/sound/soc/codecs/tfa9879.h b/sound/soc/codecs/tfa9879.h index 3408c90c4628..66c88d0396fe 100644 --- a/sound/soc/codecs/tfa9879.h +++ b/sound/soc/codecs/tfa9879.h @@ -1,14 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * tfa9879.h -- driver for NXP Semiconductors TFA9879 * * Copyright (C) 2014 Axentia Technologies AB * Author: Peter Rosin <peda@axentia.se> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * */ #ifndef _TFA9879_H diff --git a/sound/soc/codecs/tscs42xx.c b/sound/soc/codecs/tscs42xx.c index bbfc73a79b18..d18ff17719cc 100644 --- a/sound/soc/codecs/tscs42xx.c +++ b/sound/soc/codecs/tscs42xx.c @@ -12,6 +12,7 @@ #include <linux/module.h> #include <linux/delay.h> #include <linux/mutex.h> +#include <linux/clk.h> #include <sound/tlv.h> #include <sound/pcm_params.h> #include <sound/soc.h> @@ -31,7 +32,6 @@ struct tscs42xx { int bclk_ratio; int samplerate; - unsigned int blrcm; struct mutex audio_params_lock; u8 coeff_ram[COEFF_RAM_SIZE]; @@ -42,7 +42,8 @@ struct tscs42xx { struct regmap *regmap; - struct device *dev; + struct clk *sysclk; + int sysclk_src_id; }; struct coeff_ram_ctl { @@ -204,7 +205,8 @@ static int power_up_audio_plls(struct snd_soc_component *component) break; default: ret = -EINVAL; - dev_err(component->dev, "Unrecognized PLL output freq (%d)\n", ret); + dev_err(component->dev, + "Unrecognized PLL output freq (%d)\n", ret); return ret; } @@ -261,7 +263,8 @@ exit: static int coeff_ram_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { - struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); struct coeff_ram_ctl *ctl = (struct coeff_ram_ctl *)kcontrol->private_value; @@ -280,7 +283,8 @@ static int coeff_ram_get(struct snd_kcontrol *kcontrol, static int coeff_ram_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { - struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); struct coeff_ram_ctl *ctl = (struct coeff_ram_ctl *)kcontrol->private_value; @@ -363,7 +367,8 @@ static int dapm_micb_event(struct snd_soc_dapm_widget *w, static int pll_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { - struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); int ret; if (SND_SOC_DAPM_EVENT_ON(event)) @@ -377,7 +382,8 @@ static int pll_event(struct snd_soc_dapm_widget *w, static int dac_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { - struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); int ret; @@ -819,16 +825,19 @@ static int setup_sample_format(struct snd_soc_component *component, dev_err(component->dev, "Unsupported format width (%d)\n", ret); return ret; } - ret = snd_soc_component_update_bits(component, R_AIC1, RM_AIC1_WL, width); + ret = snd_soc_component_update_bits(component, + R_AIC1, RM_AIC1_WL, width); if (ret < 0) { - dev_err(component->dev, "Failed to set sample width (%d)\n", ret); + dev_err(component->dev, + "Failed to set sample width (%d)\n", ret); return ret; } return 0; } -static int setup_sample_rate(struct snd_soc_component *component, unsigned int rate) +static int setup_sample_rate(struct snd_soc_component *component, + unsigned int rate) { struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); unsigned int br, bm; @@ -881,24 +890,32 @@ static int setup_sample_rate(struct snd_soc_component *component, unsigned int r } /* DAC and ADC share bit and frame clock */ - ret = snd_soc_component_update_bits(component, R_DACSR, RM_DACSR_DBR, br); + ret = snd_soc_component_update_bits(component, + R_DACSR, RM_DACSR_DBR, br); if (ret < 0) { - dev_err(component->dev, "Failed to update register (%d)\n", ret); + dev_err(component->dev, + "Failed to update register (%d)\n", ret); return ret; } - ret = snd_soc_component_update_bits(component, R_DACSR, RM_DACSR_DBM, bm); + ret = snd_soc_component_update_bits(component, + R_DACSR, RM_DACSR_DBM, bm); if (ret < 0) { - dev_err(component->dev, "Failed to update register (%d)\n", ret); + dev_err(component->dev, + "Failed to update register (%d)\n", ret); return ret; } - ret = snd_soc_component_update_bits(component, R_ADCSR, RM_DACSR_DBR, br); + ret = snd_soc_component_update_bits(component, + R_ADCSR, RM_DACSR_DBR, br); if (ret < 0) { - dev_err(component->dev, "Failed to update register (%d)\n", ret); + dev_err(component->dev, + "Failed to update register (%d)\n", ret); return ret; } - ret = snd_soc_component_update_bits(component, R_ADCSR, RM_DACSR_DBM, bm); + ret = snd_soc_component_update_bits(component, + R_ADCSR, RM_DACSR_DBM, bm); if (ret < 0) { - dev_err(component->dev, "Failed to update register (%d)\n", ret); + dev_err(component->dev, + "Failed to update register (%d)\n", ret); return ret; } @@ -1076,7 +1093,8 @@ static int tscs42xx_hw_params(struct snd_pcm_substream *substream, ret = setup_sample_rate(component, params_rate(params)); if (ret < 0) { - dev_err(component->dev, "Failed to setup sample rate (%d)\n", ret); + dev_err(component->dev, + "Failed to setup sample rate (%d)\n", ret); return ret; } @@ -1087,7 +1105,8 @@ static inline int dac_mute(struct snd_soc_component *component) { int ret; - ret = snd_soc_component_update_bits(component, R_CNVRTR1, RM_CNVRTR1_DACMU, + ret = snd_soc_component_update_bits(component, + R_CNVRTR1, RM_CNVRTR1_DACMU, RV_CNVRTR1_DACMU_ENABLE); if (ret < 0) { dev_err(component->dev, "Failed to mute DAC (%d)\n", @@ -1102,7 +1121,8 @@ static inline int dac_unmute(struct snd_soc_component *component) { int ret; - ret = snd_soc_component_update_bits(component, R_CNVRTR1, RM_CNVRTR1_DACMU, + ret = snd_soc_component_update_bits(component, + R_CNVRTR1, RM_CNVRTR1_DACMU, RV_CNVRTR1_DACMU_DISABLE); if (ret < 0) { dev_err(component->dev, "Failed to unmute DAC (%d)\n", @@ -1117,8 +1137,8 @@ static inline int adc_mute(struct snd_soc_component *component) { int ret; - ret = snd_soc_component_update_bits(component, R_CNVRTR0, RM_CNVRTR0_ADCMU, - RV_CNVRTR0_ADCMU_ENABLE); + ret = snd_soc_component_update_bits(component, + R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_ENABLE); if (ret < 0) { dev_err(component->dev, "Failed to mute ADC (%d)\n", ret); @@ -1132,8 +1152,8 @@ static inline int adc_unmute(struct snd_soc_component *component) { int ret; - ret = snd_soc_component_update_bits(component, R_CNVRTR0, RM_CNVRTR0_ADCMU, - RV_CNVRTR0_ADCMU_DISABLE); + ret = snd_soc_component_update_bits(component, + R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_DISABLE); if (ret < 0) { dev_err(component->dev, "Failed to unmute ADC (%d)\n", ret); @@ -1171,8 +1191,8 @@ static int tscs42xx_set_dai_fmt(struct snd_soc_dai *codec_dai, /* Slave mode not supported since it needs always-on frame clock */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBM_CFM: - ret = snd_soc_component_update_bits(component, R_AIC1, RM_AIC1_MS, - RV_AIC1_MS_MASTER); + ret = snd_soc_component_update_bits(component, + R_AIC1, RM_AIC1_MS, RV_AIC1_MS_MASTER); if (ret < 0) { dev_err(component->dev, "Failed to set codec DAI master (%d)\n", ret); @@ -1211,14 +1231,18 @@ static int tscs42xx_set_dai_bclk_ratio(struct snd_soc_dai *codec_dai, return -EINVAL; } - ret = snd_soc_component_update_bits(component, R_DACSR, RM_DACSR_DBCM, value); + ret = snd_soc_component_update_bits(component, + R_DACSR, RM_DACSR_DBCM, value); if (ret < 0) { - dev_err(component->dev, "Failed to set DAC BCLK ratio (%d)\n", ret); + dev_err(component->dev, + "Failed to set DAC BCLK ratio (%d)\n", ret); return ret; } - ret = snd_soc_component_update_bits(component, R_ADCSR, RM_ADCSR_ABCM, value); + ret = snd_soc_component_update_bits(component, + R_ADCSR, RM_ADCSR_ABCM, value); if (ret < 0) { - dev_err(component->dev, "Failed to set ADC BCLK ratio (%d)\n", ret); + dev_err(component->dev, + "Failed to set ADC BCLK ratio (%d)\n", ret); return ret; } @@ -1231,13 +1255,46 @@ static int tscs42xx_set_dai_bclk_ratio(struct snd_soc_dai *codec_dai, return 0; } -static int tscs42xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, - int clk_id, unsigned int freq, int dir) +static const struct snd_soc_dai_ops tscs42xx_dai_ops = { + .hw_params = tscs42xx_hw_params, + .mute_stream = tscs42xx_mute_stream, + .set_fmt = tscs42xx_set_dai_fmt, + .set_bclk_ratio = tscs42xx_set_dai_bclk_ratio, +}; + +static int part_is_valid(struct tscs42xx *tscs42xx) { - struct snd_soc_component *component = codec_dai->component; + int val; int ret; + unsigned int reg; + + ret = regmap_read(tscs42xx->regmap, R_DEVIDH, ®); + if (ret < 0) + return ret; + + val = reg << 8; + ret = regmap_read(tscs42xx->regmap, R_DEVIDL, ®); + if (ret < 0) + return ret; + + val |= reg; + + switch (val) { + case 0x4A74: + case 0x4A73: + return true; + default: + return false; + }; +} - switch (clk_id) { +static int set_sysclk(struct snd_soc_component *component) +{ + struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); + unsigned long freq; + int ret; + + switch (tscs42xx->sysclk_src_id) { case TSCS42XX_PLL_SRC_XTAL: case TSCS42XX_PLL_SRC_MCLK1: ret = snd_soc_component_write(component, R_PLLREFSEL, @@ -1265,6 +1322,7 @@ static int tscs42xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, return -EINVAL; } + freq = clk_get_rate(tscs42xx->sysclk); ret = set_pll_ctl_from_input_freq(component, freq); if (ret < 0) { dev_err(component->dev, @@ -1275,41 +1333,13 @@ static int tscs42xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, return 0; } -static const struct snd_soc_dai_ops tscs42xx_dai_ops = { - .hw_params = tscs42xx_hw_params, - .mute_stream = tscs42xx_mute_stream, - .set_fmt = tscs42xx_set_dai_fmt, - .set_bclk_ratio = tscs42xx_set_dai_bclk_ratio, - .set_sysclk = tscs42xx_set_dai_sysclk, -}; - -static int part_is_valid(struct tscs42xx *tscs42xx) +static int tscs42xx_probe(struct snd_soc_component *component) { - int val; - int ret; - unsigned int reg; - - ret = regmap_read(tscs42xx->regmap, R_DEVIDH, ®); - if (ret < 0) - return ret; - - val = reg << 8; - ret = regmap_read(tscs42xx->regmap, R_DEVIDL, ®); - if (ret < 0) - return ret; - - val |= reg; - - switch (val) { - case 0x4A74: - case 0x4A73: - return true; - default: - return false; - }; + return set_sysclk(component); } -static struct snd_soc_component_driver soc_codec_dev_tscs42xx = { +static const struct snd_soc_component_driver soc_codec_dev_tscs42xx = { + .probe = tscs42xx_probe, .dapm_widgets = tscs42xx_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(tscs42xx_dapm_widgets), .dapm_routes = tscs42xx_intercon, @@ -1367,11 +1397,15 @@ static const struct reg_sequence tscs42xx_patch[] = { { R_AIC2, RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED }, }; +static char const * const src_names[TSCS42XX_PLL_SRC_CNT] = { + "xtal", "mclk1", "mclk2"}; + static int tscs42xx_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { struct tscs42xx *tscs42xx; - int ret = 0; + int src; + int ret; tscs42xx = devm_kzalloc(&i2c->dev, sizeof(*tscs42xx), GFP_KERNEL); if (!tscs42xx) { @@ -1381,12 +1415,29 @@ static int tscs42xx_i2c_probe(struct i2c_client *i2c, return ret; } i2c_set_clientdata(i2c, tscs42xx); - tscs42xx->dev = &i2c->dev; + + for (src = TSCS42XX_PLL_SRC_XTAL; src < TSCS42XX_PLL_SRC_CNT; src++) { + tscs42xx->sysclk = devm_clk_get(&i2c->dev, src_names[src]); + if (!IS_ERR(tscs42xx->sysclk)) { + break; + } else if (PTR_ERR(tscs42xx->sysclk) != -ENOENT) { + ret = PTR_ERR(tscs42xx->sysclk); + dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret); + return ret; + } + } + if (src == TSCS42XX_PLL_SRC_CNT) { + ret = -EINVAL; + dev_err(&i2c->dev, "Failed to get a valid clock name (%d)\n", + ret); + return ret; + } + tscs42xx->sysclk_src_id = src; tscs42xx->regmap = devm_regmap_init_i2c(i2c, &tscs42xx_regmap); if (IS_ERR(tscs42xx->regmap)) { ret = PTR_ERR(tscs42xx->regmap); - dev_err(tscs42xx->dev, "Failed to allocate regmap (%d)\n", ret); + dev_err(&i2c->dev, "Failed to allocate regmap (%d)\n", ret); return ret; } @@ -1394,21 +1445,21 @@ static int tscs42xx_i2c_probe(struct i2c_client *i2c, ret = part_is_valid(tscs42xx); if (ret <= 0) { - dev_err(tscs42xx->dev, "No valid part (%d)\n", ret); + dev_err(&i2c->dev, "No valid part (%d)\n", ret); ret = -ENODEV; return ret; } ret = regmap_write(tscs42xx->regmap, R_RESET, RV_RESET_ENABLE); if (ret < 0) { - dev_err(tscs42xx->dev, "Failed to reset device (%d)\n", ret); + dev_err(&i2c->dev, "Failed to reset device (%d)\n", ret); return ret; } ret = regmap_register_patch(tscs42xx->regmap, tscs42xx_patch, ARRAY_SIZE(tscs42xx_patch)); if (ret < 0) { - dev_err(tscs42xx->dev, "Failed to apply patch (%d)\n", ret); + dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret); return ret; } @@ -1416,10 +1467,10 @@ static int tscs42xx_i2c_probe(struct i2c_client *i2c, mutex_init(&tscs42xx->coeff_ram_lock); mutex_init(&tscs42xx->pll_lock); - ret = devm_snd_soc_register_component(tscs42xx->dev, &soc_codec_dev_tscs42xx, - &tscs42xx_dai, 1); + ret = devm_snd_soc_register_component(&i2c->dev, + &soc_codec_dev_tscs42xx, &tscs42xx_dai, 1); if (ret) { - dev_err(tscs42xx->dev, "Failed to register codec (%d)\n", ret); + dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret); return ret; } diff --git a/sound/soc/codecs/tscs42xx.h b/sound/soc/codecs/tscs42xx.h index d4a30bcbf64b..814c8f3c4a68 100644 --- a/sound/soc/codecs/tscs42xx.h +++ b/sound/soc/codecs/tscs42xx.h @@ -7,10 +7,10 @@ #define __WOOKIE_H__ enum { - TSCS42XX_PLL_SRC_NONE, TSCS42XX_PLL_SRC_XTAL, TSCS42XX_PLL_SRC_MCLK1, TSCS42XX_PLL_SRC_MCLK2, + TSCS42XX_PLL_SRC_CNT, }; #define R_HPVOLL 0x0 diff --git a/sound/soc/codecs/tscs454.c b/sound/soc/codecs/tscs454.c new file mode 100644 index 000000000000..ff85a0bf6170 --- /dev/null +++ b/sound/soc/codecs/tscs454.c @@ -0,0 +1,3497 @@ +// SPDX-License-Identifier: GPL-2.0 +// tscs454.c -- TSCS454 ALSA SoC Audio driver +// Copyright 2018 Tempo Semiconductor, Inc. +// Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com> + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/regmap.h> +#include <linux/i2c.h> +#include <linux/err.h> +#include <linux/string.h> +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/mutex.h> + +#include <sound/tlv.h> +#include <sound/pcm_params.h> +#include <sound/pcm.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> + +#include "tscs454.h" + +static const unsigned int PLL_48K_RATE = (48000 * 256); +static const unsigned int PLL_44_1K_RATE = (44100 * 256); + +#define COEFF_SIZE 3 +#define BIQUAD_COEFF_COUNT 5 +#define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT) + +#define COEFF_RAM_MAX_ADDR 0xcd +#define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1) +#define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT) + +enum { + TSCS454_DAI1_ID, + TSCS454_DAI2_ID, + TSCS454_DAI3_ID, + TSCS454_DAI_COUNT, +}; + +struct pll { + int id; + unsigned int users; + struct mutex lock; +}; + +static inline void pll_init(struct pll *pll, int id) +{ + pll->id = id; + mutex_init(&pll->lock); +} + +struct internal_rate { + struct pll *pll; +}; + +struct aif { + unsigned int id; + bool master; + struct pll *pll; +}; + +static inline void aif_init(struct aif *aif, unsigned int id) +{ + aif->id = id; +} + +struct coeff_ram { + u8 cache[COEFF_RAM_SIZE]; + bool synced; + struct mutex lock; +}; + +static inline void init_coeff_ram_cache(u8 *cache) +{ + static const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, + 0x1f, 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45, + 0x4a, 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74, + 0x79, 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3, + 0xa8, 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9}; + int i; + + for (i = 0; i < ARRAY_SIZE(norm_addrs); i++) + cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; +} + +static inline void coeff_ram_init(struct coeff_ram *ram) +{ + init_coeff_ram_cache(ram->cache); + mutex_init(&ram->lock); +} + +struct aifs_status { + u8 streams; +}; + +static inline void set_aif_status_active(struct aifs_status *status, + int aif_id, bool playback) +{ + u8 mask = 0x01 << (aif_id * 2 + !playback); + + status->streams |= mask; +} + +static inline void set_aif_status_inactive(struct aifs_status *status, + int aif_id, bool playback) +{ + u8 mask = ~(0x01 << (aif_id * 2 + !playback)); + + status->streams &= mask; +} + +static bool aifs_active(struct aifs_status *status) +{ + return status->streams; +} + +static bool aif_active(struct aifs_status *status, int aif_id) +{ + return (0x03 << aif_id * 2) & status->streams; +} + +struct tscs454 { + struct regmap *regmap; + struct aif aifs[TSCS454_DAI_COUNT]; + + struct aifs_status aifs_status; + struct mutex aifs_status_lock; + + struct pll pll1; + struct pll pll2; + struct internal_rate internal_rate; + + struct coeff_ram dac_ram; + struct coeff_ram spk_ram; + struct coeff_ram sub_ram; + + struct clk *sysclk; + int sysclk_src_id; + unsigned int bclk_freq; +}; + +struct coeff_ram_ctl { + unsigned int addr; + struct soc_bytes_ext bytes_ext; +}; + +static const struct reg_sequence tscs454_patch[] = { + /* Assign ASRC out of the box so DAI 1 just works */ + { R_AUDIOMUX1, FV_ASRCIMUX_I2S1 | FV_I2S2MUX_I2S2 }, + { R_AUDIOMUX2, FV_ASRCOMUX_I2S1 | FV_DACMUX_I2S1 | FV_I2S3MUX_I2S3 }, + { R_AUDIOMUX3, FV_CLSSDMUX_I2S1 | FV_SUBMUX_I2S1_LR }, + { R_TDMCTL0, FV_TDMMD_256 }, + { VIRT_ADDR(0x0A, 0x13), 1 << 3 }, +}; + +static bool tscs454_volatile(struct device *dev, unsigned int reg) +{ + switch (reg) { + case R_PLLSTAT: + + case R_SPKCRRDL: + case R_SPKCRRDM: + case R_SPKCRRDH: + case R_SPKCRS: + + case R_DACCRRDL: + case R_DACCRRDM: + case R_DACCRRDH: + case R_DACCRS: + + case R_SUBCRRDL: + case R_SUBCRRDM: + case R_SUBCRRDH: + case R_SUBCRS: + return true; + default: + return false; + }; +} + +static bool tscs454_writable(struct device *dev, unsigned int reg) +{ + switch (reg) { + case R_SPKCRRDL: + case R_SPKCRRDM: + case R_SPKCRRDH: + + case R_DACCRRDL: + case R_DACCRRDM: + case R_DACCRRDH: + + case R_SUBCRRDL: + case R_SUBCRRDM: + case R_SUBCRRDH: + return false; + default: + return true; + }; +} + +static bool tscs454_readable(struct device *dev, unsigned int reg) +{ + switch (reg) { + case R_SPKCRWDL: + case R_SPKCRWDM: + case R_SPKCRWDH: + + case R_DACCRWDL: + case R_DACCRWDM: + case R_DACCRWDH: + + case R_SUBCRWDL: + case R_SUBCRWDM: + case R_SUBCRWDH: + return false; + default: + return true; + }; +} + +static bool tscs454_precious(struct device *dev, unsigned int reg) +{ + switch (reg) { + case R_SPKCRWDL: + case R_SPKCRWDM: + case R_SPKCRWDH: + case R_SPKCRRDL: + case R_SPKCRRDM: + case R_SPKCRRDH: + + case R_DACCRWDL: + case R_DACCRWDM: + case R_DACCRWDH: + case R_DACCRRDL: + case R_DACCRRDM: + case R_DACCRRDH: + + case R_SUBCRWDL: + case R_SUBCRWDM: + case R_SUBCRWDH: + case R_SUBCRRDL: + case R_SUBCRRDM: + case R_SUBCRRDH: + return true; + default: + return false; + }; +} + +static const struct regmap_range_cfg tscs454_regmap_range_cfg = { + .name = "Pages", + .range_min = VIRT_BASE, + .range_max = VIRT_ADDR(0xFE, 0x02), + .selector_reg = R_PAGESEL, + .selector_mask = 0xff, + .selector_shift = 0, + .window_start = 0, + .window_len = 0x100, +}; + +static struct regmap_config const tscs454_regmap_cfg = { + .reg_bits = 8, + .val_bits = 8, + .writeable_reg = tscs454_writable, + .readable_reg = tscs454_readable, + .volatile_reg = tscs454_volatile, + .precious_reg = tscs454_precious, + .ranges = &tscs454_regmap_range_cfg, + .num_ranges = 1, + .max_register = VIRT_ADDR(0xFE, 0x02), + .cache_type = REGCACHE_RBTREE, +}; + +static inline int tscs454_data_init(struct tscs454 *tscs454, + struct i2c_client *i2c) +{ + int i; + int ret; + + tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg); + if (IS_ERR(tscs454->regmap)) { + ret = PTR_ERR(tscs454->regmap); + return ret; + } + + for (i = 0; i < TSCS454_DAI_COUNT; i++) + aif_init(&tscs454->aifs[i], i); + + mutex_init(&tscs454->aifs_status_lock); + pll_init(&tscs454->pll1, 1); + pll_init(&tscs454->pll2, 2); + + coeff_ram_init(&tscs454->dac_ram); + coeff_ram_init(&tscs454->spk_ram); + coeff_ram_init(&tscs454->sub_ram); + + return 0; +} + +struct reg_setting { + unsigned int addr; + unsigned int val; +}; + +static int coeff_ram_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + struct coeff_ram_ctl *ctl = + (struct coeff_ram_ctl *)kcontrol->private_value; + struct soc_bytes_ext *params = &ctl->bytes_ext; + u8 *coeff_ram; + struct mutex *coeff_ram_lock; + + if (strstr(kcontrol->id.name, "DAC")) { + coeff_ram = tscs454->dac_ram.cache; + coeff_ram_lock = &tscs454->dac_ram.lock; + } else if (strstr(kcontrol->id.name, "Speaker")) { + coeff_ram = tscs454->spk_ram.cache; + coeff_ram_lock = &tscs454->spk_ram.lock; + } else if (strstr(kcontrol->id.name, "Sub")) { + coeff_ram = tscs454->sub_ram.cache; + coeff_ram_lock = &tscs454->sub_ram.lock; + } else { + return -EINVAL; + } + + mutex_lock(coeff_ram_lock); + + memcpy(ucontrol->value.bytes.data, + &coeff_ram[ctl->addr * COEFF_SIZE], params->max); + + mutex_unlock(coeff_ram_lock); + + return 0; +} + +#define DACCRSTAT_MAX_TRYS 10 +static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram, + unsigned int r_stat, unsigned int r_addr, unsigned int r_wr, + unsigned int coeff_addr, unsigned int coeff_cnt) +{ + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + unsigned int val; + int cnt; + int trys; + int ret; + + for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) { + + for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) { + ret = snd_soc_component_read(component, r_stat, &val); + if (ret < 0) { + dev_err(component->dev, + "Failed to read stat (%d)\n", ret); + return ret; + } + if (!val) + break; + } + + if (trys == DACCRSTAT_MAX_TRYS) { + ret = -EIO; + dev_err(component->dev, + "Coefficient write error (%d)\n", ret); + return ret; + } + + ret = regmap_write(tscs454->regmap, r_addr, coeff_addr); + if (ret < 0) { + dev_err(component->dev, + "Failed to write dac ram address (%d)\n", ret); + return ret; + } + + ret = regmap_bulk_write(tscs454->regmap, r_wr, + &coeff_ram[coeff_addr * COEFF_SIZE], + COEFF_SIZE); + if (ret < 0) { + dev_err(component->dev, + "Failed to write dac ram (%d)\n", ret); + return ret; + } + } + + return 0; +} + +static int coeff_ram_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + struct coeff_ram_ctl *ctl = + (struct coeff_ram_ctl *)kcontrol->private_value; + struct soc_bytes_ext *params = &ctl->bytes_ext; + unsigned int coeff_cnt = params->max / COEFF_SIZE; + u8 *coeff_ram; + struct mutex *coeff_ram_lock; + bool *coeff_ram_synced; + unsigned int r_stat; + unsigned int r_addr; + unsigned int r_wr; + unsigned int val; + int ret; + + if (strstr(kcontrol->id.name, "DAC")) { + coeff_ram = tscs454->dac_ram.cache; + coeff_ram_lock = &tscs454->dac_ram.lock; + coeff_ram_synced = &tscs454->dac_ram.synced; + r_stat = R_DACCRS; + r_addr = R_DACCRADD; + r_wr = R_DACCRWDL; + } else if (strstr(kcontrol->id.name, "Speaker")) { + coeff_ram = tscs454->spk_ram.cache; + coeff_ram_lock = &tscs454->spk_ram.lock; + coeff_ram_synced = &tscs454->spk_ram.synced; + r_stat = R_SPKCRS; + r_addr = R_SPKCRADD; + r_wr = R_SPKCRWDL; + } else if (strstr(kcontrol->id.name, "Sub")) { + coeff_ram = tscs454->sub_ram.cache; + coeff_ram_lock = &tscs454->sub_ram.lock; + coeff_ram_synced = &tscs454->sub_ram.synced; + r_stat = R_SUBCRS; + r_addr = R_SUBCRADD; + r_wr = R_SUBCRWDL; + } else { + return -EINVAL; + } + + mutex_lock(coeff_ram_lock); + + *coeff_ram_synced = false; + + memcpy(&coeff_ram[ctl->addr * COEFF_SIZE], + ucontrol->value.bytes.data, params->max); + + mutex_lock(&tscs454->pll1.lock); + mutex_lock(&tscs454->pll2.lock); + + ret = snd_soc_component_read(component, R_PLLSTAT, &val); + if (ret < 0) { + dev_err(component->dev, "Failed to read PLL status (%d)\n", + ret); + goto exit; + } + if (val) { /* PLLs locked */ + ret = write_coeff_ram(component, coeff_ram, + r_stat, r_addr, r_wr, + ctl->addr, coeff_cnt); + if (ret < 0) { + dev_err(component->dev, + "Failed to flush coeff ram cache (%d)\n", ret); + goto exit; + } + *coeff_ram_synced = true; + } + + ret = 0; +exit: + mutex_unlock(&tscs454->pll2.lock); + mutex_unlock(&tscs454->pll1.lock); + mutex_unlock(coeff_ram_lock); + + return ret; +} + +static inline int coeff_ram_sync(struct snd_soc_component *component, + struct tscs454 *tscs454) +{ + int ret; + + mutex_lock(&tscs454->dac_ram.lock); + if (!tscs454->dac_ram.synced) { + ret = write_coeff_ram(component, tscs454->dac_ram.cache, + R_DACCRS, R_DACCRADD, R_DACCRWDL, + 0x00, COEFF_RAM_COEFF_COUNT); + if (ret < 0) { + mutex_unlock(&tscs454->dac_ram.lock); + return ret; + } + } + mutex_unlock(&tscs454->dac_ram.lock); + + mutex_lock(&tscs454->spk_ram.lock); + if (!tscs454->spk_ram.synced) { + ret = write_coeff_ram(component, tscs454->spk_ram.cache, + R_SPKCRS, R_SPKCRADD, R_SPKCRWDL, + 0x00, COEFF_RAM_COEFF_COUNT); + if (ret < 0) { + mutex_unlock(&tscs454->spk_ram.lock); + return ret; + } + } + mutex_unlock(&tscs454->spk_ram.lock); + + mutex_lock(&tscs454->sub_ram.lock); + if (!tscs454->sub_ram.synced) { + ret = write_coeff_ram(component, tscs454->sub_ram.cache, + R_SUBCRS, R_SUBCRADD, R_SUBCRWDL, + 0x00, COEFF_RAM_COEFF_COUNT); + if (ret < 0) { + mutex_unlock(&tscs454->sub_ram.lock); + return ret; + } + } + mutex_unlock(&tscs454->sub_ram.lock); + + return 0; +} + +#define PLL_REG_SETTINGS_COUNT 11 +struct pll_ctl { + int freq_in; + struct reg_setting settings[PLL_REG_SETTINGS_COUNT]; +}; + +#define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h) \ + { \ + .freq_in = f, \ + .settings = { \ + {R_PLL1CTL, c1}, \ + {R_PLL1RDIV, r1}, \ + {R_PLL1ODIV, o1}, \ + {R_PLL1FDIVL, f1l}, \ + {R_PLL1FDIVH, f1h}, \ + {R_PLL2CTL, c2}, \ + {R_PLL2RDIV, r2}, \ + {R_PLL2ODIV, o2}, \ + {R_PLL2FDIVL, f2l}, \ + {R_PLL2FDIVH, f2h}, \ + {R_TIMEBASE, t}, \ + }, \ + } + +static const struct pll_ctl pll_ctls[] = { + PLL_CTL(1411200, 0x05, + 0xB9, 0x07, 0x02, 0xC3, 0x04, + 0x5A, 0x02, 0x03, 0xE0, 0x01), + PLL_CTL(1536000, 0x05, + 0x5A, 0x02, 0x03, 0xE0, 0x01, + 0x5A, 0x02, 0x03, 0xB9, 0x01), + PLL_CTL(2822400, 0x0A, + 0x63, 0x07, 0x04, 0xC3, 0x04, + 0x62, 0x07, 0x03, 0x48, 0x03), + PLL_CTL(3072000, 0x0B, + 0x62, 0x07, 0x03, 0x48, 0x03, + 0x5A, 0x04, 0x03, 0xB9, 0x01), + PLL_CTL(5644800, 0x15, + 0x63, 0x0E, 0x04, 0xC3, 0x04, + 0x5A, 0x08, 0x03, 0xE0, 0x01), + PLL_CTL(6144000, 0x17, + 0x5A, 0x08, 0x03, 0xE0, 0x01, + 0x5A, 0x08, 0x03, 0xB9, 0x01), + PLL_CTL(12000000, 0x2E, + 0x5B, 0x19, 0x03, 0x00, 0x03, + 0x6A, 0x19, 0x05, 0x98, 0x04), + PLL_CTL(19200000, 0x4A, + 0x53, 0x14, 0x03, 0x80, 0x01, + 0x5A, 0x19, 0x03, 0xB9, 0x01), + PLL_CTL(22000000, 0x55, + 0x6A, 0x37, 0x05, 0x00, 0x06, + 0x62, 0x26, 0x03, 0x49, 0x02), + PLL_CTL(22579200, 0x57, + 0x62, 0x31, 0x03, 0x20, 0x03, + 0x53, 0x1D, 0x03, 0xB3, 0x01), + PLL_CTL(24000000, 0x5D, + 0x53, 0x19, 0x03, 0x80, 0x01, + 0x5B, 0x19, 0x05, 0x4C, 0x02), + PLL_CTL(24576000, 0x5F, + 0x53, 0x1D, 0x03, 0xB3, 0x01, + 0x62, 0x40, 0x03, 0x72, 0x03), + PLL_CTL(27000000, 0x68, + 0x62, 0x4B, 0x03, 0x00, 0x04, + 0x6A, 0x7D, 0x03, 0x20, 0x06), + PLL_CTL(36000000, 0x8C, + 0x5B, 0x4B, 0x03, 0x00, 0x03, + 0x6A, 0x7D, 0x03, 0x98, 0x04), + PLL_CTL(11289600, 0x2B, + 0x6A, 0x31, 0x03, 0x40, 0x06, + 0x5A, 0x12, 0x03, 0x1C, 0x02), + PLL_CTL(26000000, 0x65, + 0x63, 0x41, 0x05, 0x00, 0x06, + 0x5A, 0x26, 0x03, 0xEF, 0x01), + PLL_CTL(12288000, 0x2F, + 0x5A, 0x12, 0x03, 0x1C, 0x02, + 0x62, 0x20, 0x03, 0x72, 0x03), + PLL_CTL(40000000, 0x9B, + 0xA2, 0x7D, 0x03, 0x80, 0x04, + 0x63, 0x7D, 0x05, 0xE4, 0x06), + PLL_CTL(512000, 0x01, + 0x62, 0x01, 0x03, 0xD0, 0x02, + 0x5B, 0x01, 0x04, 0x72, 0x03), + PLL_CTL(705600, 0x02, + 0x62, 0x02, 0x03, 0x15, 0x04, + 0x62, 0x01, 0x04, 0x80, 0x02), + PLL_CTL(1024000, 0x03, + 0x62, 0x02, 0x03, 0xD0, 0x02, + 0x5B, 0x02, 0x04, 0x72, 0x03), + PLL_CTL(2048000, 0x07, + 0x62, 0x04, 0x03, 0xD0, 0x02, + 0x5B, 0x04, 0x04, 0x72, 0x03), + PLL_CTL(2400000, 0x08, + 0x62, 0x05, 0x03, 0x00, 0x03, + 0x63, 0x05, 0x05, 0x98, 0x04), +}; + +static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in) +{ + int i; + struct pll_ctl const *pll_ctl = NULL; + + for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i) + if (pll_ctls[i].freq_in == freq_in) { + pll_ctl = &pll_ctls[i]; + break; + } + + return pll_ctl; +} + +enum { + PLL_INPUT_XTAL = 0, + PLL_INPUT_MCLK1, + PLL_INPUT_MCLK2, + PLL_INPUT_BCLK, +}; + +static int set_sysclk(struct snd_soc_component *component) +{ + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + struct pll_ctl const *pll_ctl; + unsigned long freq; + int i; + int ret; + + if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) + freq = clk_get_rate(tscs454->sysclk); + else + freq = tscs454->bclk_freq; + pll_ctl = get_pll_ctl(freq); + if (!pll_ctl) { + ret = -EINVAL; + dev_err(component->dev, + "Invalid PLL input %lu (%d)\n", freq, ret); + return ret; + } + + for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) { + ret = snd_soc_component_write(component, + pll_ctl->settings[i].addr, + pll_ctl->settings[i].val); + if (ret < 0) { + dev_err(component->dev, + "Failed to set pll setting (%d)\n", + ret); + return ret; + } + } + + return 0; +} + +static inline void reserve_pll(struct pll *pll) +{ + mutex_lock(&pll->lock); + pll->users++; + mutex_unlock(&pll->lock); +} + +static inline void free_pll(struct pll *pll) +{ + mutex_lock(&pll->lock); + pll->users--; + mutex_unlock(&pll->lock); +} + +static int pll_connected(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(source->dapm); + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + int users; + + if (strstr(source->name, "PLL 1")) { + mutex_lock(&tscs454->pll1.lock); + users = tscs454->pll1.users; + mutex_unlock(&tscs454->pll1.lock); + dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__, + users); + } else { + mutex_lock(&tscs454->pll2.lock); + users = tscs454->pll2.users; + mutex_unlock(&tscs454->pll2.lock); + dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__, + users); + } + + return users; +} + +/* + * PLL must be enabled after power up and must be disabled before power down + * for proper clock switching. + */ +static int pll_power_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + bool enable; + bool pll1; + unsigned int msk; + unsigned int val; + int ret; + + if (strstr(w->name, "PLL 1")) + pll1 = true; + else + pll1 = false; + + msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN; + + if (event == SND_SOC_DAPM_POST_PMU) + enable = true; + else + enable = false; + + if (enable) + val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE; + else + val = pll1 ? FV_PLL1CLKEN_DISABLE : FV_PLL2CLKEN_DISABLE; + + ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val); + if (ret < 0) { + dev_err(component->dev, "Failed to %s PLL %d (%d)\n", + enable ? "enable" : "disable", + pll1 ? 1 : 2, + ret); + return ret; + } + + if (enable) { + msleep(20); // Wait for lock + ret = coeff_ram_sync(component, tscs454); + if (ret < 0) { + dev_err(component->dev, + "Failed to sync coeff ram (%d)\n", ret); + return ret; + } + } + + return 0; +} + +static inline int aif_set_master(struct snd_soc_component *component, + unsigned int aif_id, bool master) +{ + unsigned int reg; + unsigned int mask; + unsigned int val; + int ret; + + switch (aif_id) { + case TSCS454_DAI1_ID: + reg = R_I2SP1CTL; + break; + case TSCS454_DAI2_ID: + reg = R_I2SP2CTL; + break; + case TSCS454_DAI3_ID: + reg = R_I2SP3CTL; + break; + default: + ret = -ENODEV; + dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret); + return ret; + } + mask = FM_I2SPCTL_PORTMS; + val = master ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE; + + ret = snd_soc_component_update_bits(component, reg, mask, val); + if (ret < 0) { + dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n", + aif_id, master ? "master" : "slave", ret); + return ret; + } + + return 0; +} + +static inline +int aif_prepare(struct snd_soc_component *component, struct aif *aif) +{ + int ret; + + ret = aif_set_master(component, aif->id, aif->master); + if (ret < 0) + return ret; + + return 0; +} + +static inline int aif_free(struct snd_soc_component *component, + struct aif *aif, bool playback) +{ + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + + mutex_lock(&tscs454->aifs_status_lock); + + dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id); + + set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback); + + dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n", + aif->id, tscs454->aifs_status.streams); + + if (!aif_active(&tscs454->aifs_status, aif->id)) { + /* Do config in slave mode */ + aif_set_master(component, aif->id, false); + dev_dbg(component->dev, "Freeing pll %d from aif %d\n", + aif->pll->id, aif->id); + free_pll(aif->pll); + } + + if (!aifs_active(&tscs454->aifs_status)) { + dev_dbg(component->dev, "Freeing pll %d from ir\n", + tscs454->internal_rate.pll->id); + free_pll(tscs454->internal_rate.pll); + } + + mutex_unlock(&tscs454->aifs_status_lock); + + return 0; +} + +/* R_PLLCTL PG 0 ADDR 0x15 */ +static char const * const bclk_sel_txt[] = { + "BCLK 1", "BCLK 2", "BCLK 3"}; + +static struct soc_enum const bclk_sel_enum = + SOC_ENUM_SINGLE(R_PLLCTL, FB_PLLCTL_BCLKSEL, + ARRAY_SIZE(bclk_sel_txt), bclk_sel_txt); + +/* R_ISRC PG 0 ADDR 0x16 */ +static char const * const isrc_br_txt[] = { + "44.1kHz", "48kHz"}; + +static struct soc_enum const isrc_br_enum = + SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBR, + ARRAY_SIZE(isrc_br_txt), isrc_br_txt); + +static char const * const isrc_bm_txt[] = { + "0.25x", "0.5x", "1.0x", "2.0x"}; + +static struct soc_enum const isrc_bm_enum = + SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBM, + ARRAY_SIZE(isrc_bm_txt), isrc_bm_txt); + +/* R_SCLKCTL PG 0 ADDR 0x18 */ +static char const * const modular_rate_txt[] = { + "Reserved", "Half", "Full", "Auto",}; + +static struct soc_enum const adc_modular_rate_enum = + SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_ASDM, + ARRAY_SIZE(modular_rate_txt), modular_rate_txt); + +static struct soc_enum const dac_modular_rate_enum = + SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_DSDM, + ARRAY_SIZE(modular_rate_txt), modular_rate_txt); + +/* R_I2SIDCTL PG 0 ADDR 0x38 */ +static char const * const data_ctrl_txt[] = { + "L/R", "L/L", "R/R", "R/L"}; + +static struct soc_enum const data_in_ctrl_enums[] = { + SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI1DCTL, + ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), + SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI2DCTL, + ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), + SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI3DCTL, + ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), +}; + +/* R_I2SODCTL PG 0 ADDR 0x39 */ +static struct soc_enum const data_out_ctrl_enums[] = { + SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO1DCTL, + ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), + SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO2DCTL, + ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), + SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO3DCTL, + ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), +}; + +/* R_AUDIOMUX1 PG 0 ADDR 0x3A */ +static char const * const asrc_mux_txt[] = { + "None", "DAI 1", "DAI 2", "DAI 3"}; + +static struct soc_enum const asrc_in_mux_enum = + SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_ASRCIMUX, + ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt); + +static char const * const dai_mux_txt[] = { + "CH 0_1", "CH 2_3", "CH 4_5", "ADC/DMic 1", + "DMic 2", "ClassD", "DAC", "Sub"}; + +static struct soc_enum const dai2_mux_enum = + SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S2MUX, + ARRAY_SIZE(dai_mux_txt), dai_mux_txt); + +static struct snd_kcontrol_new const dai2_mux_dapm_enum = + SOC_DAPM_ENUM("DAI 2 Mux", dai2_mux_enum); + +static struct soc_enum const dai1_mux_enum = + SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S1MUX, + ARRAY_SIZE(dai_mux_txt), dai_mux_txt); + +static struct snd_kcontrol_new const dai1_mux_dapm_enum = + SOC_DAPM_ENUM("DAI 1 Mux", dai1_mux_enum); + +/* R_AUDIOMUX2 PG 0 ADDR 0x3B */ +static struct soc_enum const asrc_out_mux_enum = + SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_ASRCOMUX, + ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt); + +static struct soc_enum const dac_mux_enum = + SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_DACMUX, + ARRAY_SIZE(dai_mux_txt), dai_mux_txt); + +static struct snd_kcontrol_new const dac_mux_dapm_enum = + SOC_DAPM_ENUM("DAC Mux", dac_mux_enum); + +static struct soc_enum const dai3_mux_enum = + SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_I2S3MUX, + ARRAY_SIZE(dai_mux_txt), dai_mux_txt); + +static struct snd_kcontrol_new const dai3_mux_dapm_enum = + SOC_DAPM_ENUM("DAI 3 Mux", dai3_mux_enum); + +/* R_AUDIOMUX3 PG 0 ADDR 0x3C */ +static char const * const sub_mux_txt[] = { + "CH 0", "CH 1", "CH 0 + 1", + "CH 2", "CH 3", "CH 2 + 3", + "CH 4", "CH 5", "CH 4 + 5", + "ADC/DMic 1 Left", "ADC/DMic 1 Right", + "ADC/DMic 1 Left Plus Right", + "DMic 2 Left", "DMic 2 Right", "DMic 2 Left Plus Right", + "ClassD Left", "ClassD Right", "ClassD Left Plus Right"}; + +static struct soc_enum const sub_mux_enum = + SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_SUBMUX, + ARRAY_SIZE(sub_mux_txt), sub_mux_txt); + +static struct snd_kcontrol_new const sub_mux_dapm_enum = + SOC_DAPM_ENUM("Sub Mux", sub_mux_enum); + +static struct soc_enum const classd_mux_enum = + SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_CLSSDMUX, + ARRAY_SIZE(dai_mux_txt), dai_mux_txt); + +static struct snd_kcontrol_new const classd_mux_dapm_enum = + SOC_DAPM_ENUM("ClassD Mux", classd_mux_enum); + +/* R_HSDCTL1 PG 1 ADDR 0x01 */ +static char const * const jack_type_txt[] = { + "3 Terminal", "4 Terminal"}; + +static struct soc_enum const hp_jack_type_enum = + SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HPJKTYPE, + ARRAY_SIZE(jack_type_txt), jack_type_txt); + +static char const * const hs_det_pol_txt[] = { + "Rising", "Falling"}; + +static struct soc_enum const hs_det_pol_enum = + SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HSDETPOL, + ARRAY_SIZE(hs_det_pol_txt), hs_det_pol_txt); + +/* R_HSDCTL1 PG 1 ADDR 0x02 */ +static char const * const hs_mic_bias_force_txt[] = { + "Off", "Ring", "Sleeve"}; + +static struct soc_enum const hs_mic_bias_force_enum = + SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FMICBIAS1, + ARRAY_SIZE(hs_mic_bias_force_txt), + hs_mic_bias_force_txt); + +static char const * const plug_type_txt[] = { + "OMTP", "CTIA", "Reserved", "Headphone"}; + +static struct soc_enum const plug_type_force_enum = + SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FPLUGTYPE, + ARRAY_SIZE(plug_type_txt), plug_type_txt); + + +/* R_CH0AIC PG 1 ADDR 0x06 */ +static char const * const in_bst_mux_txt[] = { + "Input 1", "Input 2", "Input 3", "D2S"}; + +static struct soc_enum const in_bst_mux_ch0_enum = + SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_INSELL, + ARRAY_SIZE(in_bst_mux_txt), + in_bst_mux_txt); +static struct snd_kcontrol_new const in_bst_mux_ch0_dapm_enum = + SOC_DAPM_ENUM("Input Boost Channel 0 Enum", + in_bst_mux_ch0_enum); + +static DECLARE_TLV_DB_SCALE(in_bst_vol_tlv_arr, 0, 1000, 0); + +static char const * const adc_mux_txt[] = { + "Input 1 Boost Bypass", "Input 2 Boost Bypass", + "Input 3 Boost Bypass", "Input Boost"}; + +static struct soc_enum const adc_mux_ch0_enum = + SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_LADCIN, + ARRAY_SIZE(adc_mux_txt), adc_mux_txt); +static struct snd_kcontrol_new const adc_mux_ch0_dapm_enum = + SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum); + +static char const * const in_proc_mux_txt[] = { + "ADC", "DMic"}; + +static struct soc_enum const in_proc_ch0_enum = + SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_IPCH0S, + ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt); +static struct snd_kcontrol_new const in_proc_mux_ch0_dapm_enum = + SOC_DAPM_ENUM("Input Processor Channel 0 Enum", + in_proc_ch0_enum); + +/* R_CH1AIC PG 1 ADDR 0x07 */ +static struct soc_enum const in_bst_mux_ch1_enum = + SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_INSELR, + ARRAY_SIZE(in_bst_mux_txt), + in_bst_mux_txt); +static struct snd_kcontrol_new const in_bst_mux_ch1_dapm_enum = + SOC_DAPM_ENUM("Input Boost Channel 1 Enum", + in_bst_mux_ch1_enum); + +static struct soc_enum const adc_mux_ch1_enum = + SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_RADCIN, + ARRAY_SIZE(adc_mux_txt), adc_mux_txt); +static struct snd_kcontrol_new const adc_mux_ch1_dapm_enum = + SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum); + +static struct soc_enum const in_proc_ch1_enum = + SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_IPCH1S, + ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt); +static struct snd_kcontrol_new const in_proc_mux_ch1_dapm_enum = + SOC_DAPM_ENUM("Input Processor Channel 1 Enum", + in_proc_ch1_enum); + +/* R_ICTL0 PG 1 ADDR 0x0A */ +static char const * const pol_txt[] = { + "Normal", "Invert"}; + +static struct soc_enum const in_pol_ch1_enum = + SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN0POL, + ARRAY_SIZE(pol_txt), pol_txt); + +static struct soc_enum const in_pol_ch0_enum = + SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN1POL, + ARRAY_SIZE(pol_txt), pol_txt); + +static char const * const in_proc_ch_sel_txt[] = { + "Normal", "Mono Mix to Channel 0", + "Mono Mix to Channel 1", "Add"}; + +static struct soc_enum const in_proc_ch01_sel_enum = + SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_INPCH10SEL, + ARRAY_SIZE(in_proc_ch_sel_txt), + in_proc_ch_sel_txt); + +/* R_ICTL1 PG 1 ADDR 0x0B */ +static struct soc_enum const in_pol_ch3_enum = + SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN2POL, + ARRAY_SIZE(pol_txt), pol_txt); + +static struct soc_enum const in_pol_ch2_enum = + SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN3POL, + ARRAY_SIZE(pol_txt), pol_txt); + +static struct soc_enum const in_proc_ch23_sel_enum = + SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_INPCH32SEL, + ARRAY_SIZE(in_proc_ch_sel_txt), + in_proc_ch_sel_txt); + +/* R_MICBIAS PG 1 ADDR 0x0C */ +static char const * const mic_bias_txt[] = { + "2.5V", "2.1V", "1.8V", "Vdd"}; + +static struct soc_enum const mic_bias_2_enum = + SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV2, + ARRAY_SIZE(mic_bias_txt), mic_bias_txt); + +static struct soc_enum const mic_bias_1_enum = + SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV1, + ARRAY_SIZE(mic_bias_txt), mic_bias_txt); + +/* R_PGACTL0 PG 1 ADDR 0x0D */ +/* R_PGACTL1 PG 1 ADDR 0x0E */ +/* R_PGACTL2 PG 1 ADDR 0x0F */ +/* R_PGACTL3 PG 1 ADDR 0x10 */ +static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0); + +/* R_ICH0VOL PG1 ADDR 0x12 */ +/* R_ICH1VOL PG1 ADDR 0x13 */ +/* R_ICH2VOL PG1 ADDR 0x14 */ +/* R_ICH3VOL PG1 ADDR 0x15 */ +static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400); + +/* R_ASRCILVOL PG1 ADDR 0x16 */ +/* R_ASRCIRVOL PG1 ADDR 0x17 */ +/* R_ASRCOLVOL PG1 ADDR 0x18 */ +/* R_ASRCORVOL PG1 ADDR 0x19 */ +static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600); + +/* R_ALCCTL0 PG1 ADDR 0x1D */ +static char const * const alc_mode_txt[] = { + "ALC", "Limiter"}; + +static struct soc_enum const alc_mode_enum = + SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCMODE, + ARRAY_SIZE(alc_mode_txt), alc_mode_txt); + +static char const * const alc_ref_text[] = { + "Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"}; + +static struct soc_enum const alc_ref_enum = + SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCREF, + ARRAY_SIZE(alc_ref_text), alc_ref_text); + +/* R_ALCCTL1 PG 1 ADDR 0x1E */ +static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0); +static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0); + +/* R_ALCCTL2 PG 1 ADDR 0x1F */ +static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0); + +/* R_NGATE PG 1 ADDR 0x21 */ +static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0); + +static char const * const ngate_type_txt[] = { + "PGA Constant", "ADC Mute"}; + +static struct soc_enum const ngate_type_enum = + SOC_ENUM_SINGLE(R_NGATE, FB_NGATE_NGG, + ARRAY_SIZE(ngate_type_txt), ngate_type_txt); + +/* R_DMICCTL PG 1 ADDR 0x22 */ +static char const * const dmic_mono_sel_txt[] = { + "Stereo", "Mono"}; + +static struct soc_enum const dmic_mono_sel_enum = + SOC_ENUM_SINGLE(R_DMICCTL, FB_DMICCTL_DMONO, + ARRAY_SIZE(dmic_mono_sel_txt), dmic_mono_sel_txt); + +/* R_DACCTL PG 2 ADDR 0x01 */ +static struct soc_enum const dac_pol_r_enum = + SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLR, + ARRAY_SIZE(pol_txt), pol_txt); + +static struct soc_enum const dac_pol_l_enum = + SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLL, + ARRAY_SIZE(pol_txt), pol_txt); + +static char const * const dac_dith_txt[] = { + "Half", "Full", "Disabled", "Static"}; + +static struct soc_enum const dac_dith_enum = + SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACDITH, + ARRAY_SIZE(dac_dith_txt), dac_dith_txt); + +/* R_SPKCTL PG 2 ADDR 0x02 */ +static struct soc_enum const spk_pol_r_enum = + SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLR, + ARRAY_SIZE(pol_txt), pol_txt); + +static struct soc_enum const spk_pol_l_enum = + SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLL, + ARRAY_SIZE(pol_txt), pol_txt); + +/* R_SUBCTL PG 2 ADDR 0x03 */ +static struct soc_enum const sub_pol_enum = + SOC_ENUM_SINGLE(R_SUBCTL, FB_SUBCTL_SUBPOL, + ARRAY_SIZE(pol_txt), pol_txt); + +/* R_MVOLL PG 2 ADDR 0x08 */ +/* R_MVOLR PG 2 ADDR 0x09 */ +static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0); + +/* R_HPVOLL PG 2 ADDR 0x0A */ +/* R_HPVOLR PG 2 ADDR 0x0B */ +static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0); + +/* R_SPKVOLL PG 2 ADDR 0x0C */ +/* R_SPKVOLR PG 2 ADDR 0x0D */ +static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0); + +/* R_SPKEQFILT PG 3 ADDR 0x01 */ +static char const * const eq_txt[] = { + "Pre Scale", + "Pre Scale + EQ Band 0", + "Pre Scale + EQ Band 0 - 1", + "Pre Scale + EQ Band 0 - 2", + "Pre Scale + EQ Band 0 - 3", + "Pre Scale + EQ Band 0 - 4", + "Pre Scale + EQ Band 0 - 5", +}; + +static struct soc_enum const spk_eq_enums[] = { + SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ2BE, + ARRAY_SIZE(eq_txt), eq_txt), + SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ1BE, + ARRAY_SIZE(eq_txt), eq_txt), +}; + +/* R_SPKMBCCTL PG 3 ADDR 0x0B */ +static char const * const lvl_mode_txt[] = { + "Average", "Peak"}; + +static struct soc_enum const spk_mbc3_lvl_det_mode_enum = + SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE3, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); + +static char const * const win_sel_txt[] = { + "512", "64"}; + +static struct soc_enum const spk_mbc3_win_sel_enum = + SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL3, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +static struct soc_enum const spk_mbc2_lvl_det_mode_enum = + SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE2, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); + +static struct soc_enum const spk_mbc2_win_sel_enum = + SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL2, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +static struct soc_enum const spk_mbc1_lvl_det_mode_enum = + SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE1, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); + +static struct soc_enum const spk_mbc1_win_sel_enum = + SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL1, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +/* R_SPKMBCMUG1 PG 3 ADDR 0x0C */ +static struct soc_enum const spk_mbc1_phase_pol_enum = + SOC_ENUM_SINGLE(R_SPKMBCMUG1, FB_SPKMBCMUG_PHASE, + ARRAY_SIZE(pol_txt), pol_txt); + +static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0); + +/* R_SPKMBCTHR1 PG 3 ADDR 0x0D */ +static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0); + +/* R_SPKMBCRAT1 PG 3 ADDR 0x0E */ +static char const * const comp_rat_txt[] = { + "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1", + "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1", + "15:1", "16:1", "17:1", "18:1", "19:1", "20:1"}; + +static struct soc_enum const spk_mbc1_comp_rat_enum = + SOC_ENUM_SINGLE(R_SPKMBCRAT1, FB_SPKMBCRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_SPKMBCMUG2 PG 3 ADDR 0x13 */ +static struct soc_enum const spk_mbc2_phase_pol_enum = + SOC_ENUM_SINGLE(R_SPKMBCMUG2, FB_SPKMBCMUG_PHASE, + ARRAY_SIZE(pol_txt), pol_txt); + +/* R_SPKMBCRAT2 PG 3 ADDR 0x15 */ +static struct soc_enum const spk_mbc2_comp_rat_enum = + SOC_ENUM_SINGLE(R_SPKMBCRAT2, FB_SPKMBCRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_SPKMBCMUG3 PG 3 ADDR 0x1A */ +static struct soc_enum const spk_mbc3_phase_pol_enum = + SOC_ENUM_SINGLE(R_SPKMBCMUG3, FB_SPKMBCMUG_PHASE, + ARRAY_SIZE(pol_txt), pol_txt); + +/* R_SPKMBCRAT3 PG 3 ADDR 0x1C */ +static struct soc_enum const spk_mbc3_comp_rat_enum = + SOC_ENUM_SINGLE(R_SPKMBCRAT3, FB_SPKMBCRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_SPKCLECTL PG 3 ADDR 0x21 */ +static struct soc_enum const spk_cle_lvl_mode_enum = + SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_LVLMODE, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); + +static struct soc_enum const spk_cle_win_sel_enum = + SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_WINSEL, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +/* R_SPKCLEMUG PG 3 ADDR 0x22 */ +static DECLARE_TLV_DB_MINMAX(cle_mug_tlv_arr, 0, 4650); + +/* R_SPKCOMPRAT PG 3 ADDR 0x24 */ +static struct soc_enum const spk_comp_rat_enum = + SOC_ENUM_SINGLE(R_SPKCOMPRAT, FB_SPKCOMPRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_SPKEXPTHR PG 3 ADDR 0x2F */ +static char const * const exp_rat_txt[] = { + "Reserved", "Reserved", "1:2", "1:3", + "1:4", "1:5", "1:6", "1:7"}; + +static struct soc_enum const spk_exp_rat_enum = + SOC_ENUM_SINGLE(R_SPKEXPRAT, FB_SPKEXPRAT_RATIO, + ARRAY_SIZE(exp_rat_txt), exp_rat_txt); + +/* R_DACEQFILT PG 4 ADDR 0x01 */ +static struct soc_enum const dac_eq_enums[] = { + SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ2BE, + ARRAY_SIZE(eq_txt), eq_txt), + SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ1BE, + ARRAY_SIZE(eq_txt), eq_txt), +}; + +/* R_DACMBCCTL PG 4 ADDR 0x0B */ +static struct soc_enum const dac_mbc3_lvl_det_mode_enum = + SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); + +static struct soc_enum const dac_mbc3_win_sel_enum = + SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +static struct soc_enum const dac_mbc2_lvl_det_mode_enum = + SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); + +static struct soc_enum const dac_mbc2_win_sel_enum = + SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +static struct soc_enum const dac_mbc1_lvl_det_mode_enum = + SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); + +static struct soc_enum const dac_mbc1_win_sel_enum = + SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +/* R_DACMBCMUG1 PG 4 ADDR 0x0C */ +static struct soc_enum const dac_mbc1_phase_pol_enum = + SOC_ENUM_SINGLE(R_DACMBCMUG1, FB_DACMBCMUG_PHASE, + ARRAY_SIZE(pol_txt), pol_txt); + +/* R_DACMBCRAT1 PG 4 ADDR 0x0E */ +static struct soc_enum const dac_mbc1_comp_rat_enum = + SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_DACMBCMUG2 PG 4 ADDR 0x13 */ +static struct soc_enum const dac_mbc2_phase_pol_enum = + SOC_ENUM_SINGLE(R_DACMBCMUG2, FB_DACMBCMUG_PHASE, + ARRAY_SIZE(pol_txt), pol_txt); + +/* R_DACMBCRAT2 PG 4 ADDR 0x15 */ +static struct soc_enum const dac_mbc2_comp_rat_enum = + SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_DACMBCMUG3 PG 4 ADDR 0x1A */ +static struct soc_enum const dac_mbc3_phase_pol_enum = + SOC_ENUM_SINGLE(R_DACMBCMUG3, FB_DACMBCMUG_PHASE, + ARRAY_SIZE(pol_txt), pol_txt); + +/* R_DACMBCRAT3 PG 4 ADDR 0x1C */ +static struct soc_enum const dac_mbc3_comp_rat_enum = + SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_DACCLECTL PG 4 ADDR 0x21 */ +static struct soc_enum const dac_cle_lvl_mode_enum = + SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_LVLMODE, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); + +static struct soc_enum const dac_cle_win_sel_enum = + SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_WINSEL, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +/* R_DACCOMPRAT PG 4 ADDR 0x24 */ +static struct soc_enum const dac_comp_rat_enum = + SOC_ENUM_SINGLE(R_DACCOMPRAT, FB_DACCOMPRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_DACEXPRAT PG 4 ADDR 0x30 */ +static struct soc_enum const dac_exp_rat_enum = + SOC_ENUM_SINGLE(R_DACEXPRAT, FB_DACEXPRAT_RATIO, + ARRAY_SIZE(exp_rat_txt), exp_rat_txt); + +/* R_SUBEQFILT PG 5 ADDR 0x01 */ +static struct soc_enum const sub_eq_enums[] = { + SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ2BE, + ARRAY_SIZE(eq_txt), eq_txt), + SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ1BE, + ARRAY_SIZE(eq_txt), eq_txt), +}; + +/* R_SUBMBCCTL PG 5 ADDR 0x0B */ +static struct soc_enum const sub_mbc3_lvl_det_mode_enum = + SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE3, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); + +static struct soc_enum const sub_mbc3_win_sel_enum = + SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL3, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +static struct soc_enum const sub_mbc2_lvl_det_mode_enum = + SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE2, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); + +static struct soc_enum const sub_mbc2_win_sel_enum = + SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL2, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +static struct soc_enum const sub_mbc1_lvl_det_mode_enum = + SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE1, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); + +static struct soc_enum const sub_mbc1_win_sel_enum = + SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL1, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +/* R_SUBMBCMUG1 PG 5 ADDR 0x0C */ +static struct soc_enum const sub_mbc1_phase_pol_enum = + SOC_ENUM_SINGLE(R_SUBMBCMUG1, FB_SUBMBCMUG_PHASE, + ARRAY_SIZE(pol_txt), pol_txt); + +/* R_SUBMBCRAT1 PG 5 ADDR 0x0E */ +static struct soc_enum const sub_mbc1_comp_rat_enum = + SOC_ENUM_SINGLE(R_SUBMBCRAT1, FB_SUBMBCRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_SUBMBCMUG2 PG 5 ADDR 0x13 */ +static struct soc_enum const sub_mbc2_phase_pol_enum = + SOC_ENUM_SINGLE(R_SUBMBCMUG2, FB_SUBMBCMUG_PHASE, + ARRAY_SIZE(pol_txt), pol_txt); + +/* R_SUBMBCRAT2 PG 5 ADDR 0x15 */ +static struct soc_enum const sub_mbc2_comp_rat_enum = + SOC_ENUM_SINGLE(R_SUBMBCRAT2, FB_SUBMBCRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_SUBMBCMUG3 PG 5 ADDR 0x1A */ +static struct soc_enum const sub_mbc3_phase_pol_enum = + SOC_ENUM_SINGLE(R_SUBMBCMUG3, FB_SUBMBCMUG_PHASE, + ARRAY_SIZE(pol_txt), pol_txt); + +/* R_SUBMBCRAT3 PG 5 ADDR 0x1C */ +static struct soc_enum const sub_mbc3_comp_rat_enum = + SOC_ENUM_SINGLE(R_SUBMBCRAT3, FB_SUBMBCRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_SUBCLECTL PG 5 ADDR 0x21 */ +static struct soc_enum const sub_cle_lvl_mode_enum = + SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_LVLMODE, + ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); +static struct soc_enum const sub_cle_win_sel_enum = + SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_WINSEL, + ARRAY_SIZE(win_sel_txt), win_sel_txt); + +/* R_SUBCOMPRAT PG 5 ADDR 0x24 */ +static struct soc_enum const sub_comp_rat_enum = + SOC_ENUM_SINGLE(R_SUBCOMPRAT, FB_SUBCOMPRAT_RATIO, + ARRAY_SIZE(comp_rat_txt), comp_rat_txt); + +/* R_SUBEXPRAT PG 5 ADDR 0x30 */ +static struct soc_enum const sub_exp_rat_enum = + SOC_ENUM_SINGLE(R_SUBEXPRAT, FB_SUBEXPRAT_RATIO, + ARRAY_SIZE(exp_rat_txt), exp_rat_txt); + +static int bytes_info_ext(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *ucontrol) +{ + struct coeff_ram_ctl *ctl = + (struct coeff_ram_ctl *)kcontrol->private_value; + struct soc_bytes_ext *params = &ctl->bytes_ext; + + ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; + ucontrol->count = params->max; + + return 0; +} + +/* CH 0_1 Input Mux */ +static char const * const ch_0_1_mux_txt[] = {"DAI 1", "TDM 0_1"}; + +static struct soc_enum const ch_0_1_mux_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, + ARRAY_SIZE(ch_0_1_mux_txt), ch_0_1_mux_txt); + +static struct snd_kcontrol_new const ch_0_1_mux_dapm_enum = + SOC_DAPM_ENUM("CH 0_1 Input Mux", ch_0_1_mux_enum); + +/* CH 2_3 Input Mux */ +static char const * const ch_2_3_mux_txt[] = {"DAI 2", "TDM 2_3"}; + +static struct soc_enum const ch_2_3_mux_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, + ARRAY_SIZE(ch_2_3_mux_txt), ch_2_3_mux_txt); + +static struct snd_kcontrol_new const ch_2_3_mux_dapm_enum = + SOC_DAPM_ENUM("CH 2_3 Input Mux", ch_2_3_mux_enum); + +/* CH 4_5 Input Mux */ +static char const * const ch_4_5_mux_txt[] = {"DAI 3", "TDM 4_5"}; + +static struct soc_enum const ch_4_5_mux_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, + ARRAY_SIZE(ch_4_5_mux_txt), ch_4_5_mux_txt); + +static struct snd_kcontrol_new const ch_4_5_mux_dapm_enum = + SOC_DAPM_ENUM("CH 4_5 Input Mux", ch_4_5_mux_enum); + +#define COEFF_RAM_CTL(xname, xcount, xaddr) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = bytes_info_ext, \ + .get = coeff_ram_get, .put = coeff_ram_put, \ + .private_value = (unsigned long)&(struct coeff_ram_ctl) { \ + .addr = xaddr, \ + .bytes_ext = {.max = xcount, }, \ + } \ +} + +static struct snd_kcontrol_new const tscs454_snd_controls[] = { + /* R_PLLCTL PG 0 ADDR 0x15 */ + SOC_ENUM("PLL BCLK Input", bclk_sel_enum), + /* R_ISRC PG 0 ADDR 0x16 */ + SOC_ENUM("Internal Rate", isrc_br_enum), + SOC_ENUM("Internal Rate Multiple", isrc_bm_enum), + /* R_SCLKCTL PG 0 ADDR 0x18 */ + SOC_ENUM("ADC Modular Rate", adc_modular_rate_enum), + SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum), + /* R_ASRC PG 0 ADDR 0x28 */ + SOC_SINGLE("ASRC Out High Bandwidth Switch", + R_ASRC, FB_ASRC_ASRCOBW, 1, 0), + SOC_SINGLE("ASRC In High Bandwidth Switch", + R_ASRC, FB_ASRC_ASRCIBW, 1, 0), + /* R_I2SIDCTL PG 0 ADDR 0x38 */ + SOC_ENUM("I2S 1 Data In Control", data_in_ctrl_enums[0]), + SOC_ENUM("I2S 2 Data In Control", data_in_ctrl_enums[1]), + SOC_ENUM("I2S 3 Data In Control", data_in_ctrl_enums[2]), + /* R_I2SODCTL PG 0 ADDR 0x39 */ + SOC_ENUM("I2S 1 Data Out Control", data_out_ctrl_enums[0]), + SOC_ENUM("I2S 2 Data Out Control", data_out_ctrl_enums[1]), + SOC_ENUM("I2S 3 Data Out Control", data_out_ctrl_enums[2]), + /* R_AUDIOMUX1 PG 0 ADDR 0x3A */ + SOC_ENUM("ASRC In", asrc_in_mux_enum), + /* R_AUDIOMUX2 PG 0 ADDR 0x3B */ + SOC_ENUM("ASRC Out", asrc_out_mux_enum), + /* R_HSDCTL1 PG 1 ADDR 0x01 */ + SOC_ENUM("Headphone Jack Type", hp_jack_type_enum), + SOC_ENUM("Headset Detection Polarity", hs_det_pol_enum), + SOC_SINGLE("Headphone Detection Switch", + R_HSDCTL1, FB_HSDCTL1_HPID_EN, 1, 0), + SOC_SINGLE("Headset OMTP/CTIA Switch", + R_HSDCTL1, FB_HSDCTL1_GBLHS_EN, 1, 0), + /* R_HSDCTL1 PG 1 ADDR 0x02 */ + SOC_ENUM("Headset Mic Bias Force", hs_mic_bias_force_enum), + SOC_SINGLE("Manual Mic Bias Switch", + R_HSDCTL2, FB_HSDCTL2_MB1MODE, 1, 0), + SOC_SINGLE("Ring/Sleeve Auto Switch", + R_HSDCTL2, FB_HSDCTL2_SWMODE, 1, 0), + SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum), + /* R_CH0AIC PG 1 ADDR 0x06 */ + SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC, + FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), + /* R_CH1AIC PG 1 ADDR 0x07 */ + SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC, + FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), + /* R_CH2AIC PG 1 ADDR 0x08 */ + SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC, + FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), + /* R_CH3AIC PG 1 ADDR 0x09 */ + SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC, + FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), + /* R_ICTL0 PG 1 ADDR 0x0A */ + SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum), + SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum), + SOC_ENUM("Input Processor Channel 0/1 Operation", + in_proc_ch01_sel_enum), + SOC_SINGLE("Input Channel 1 Mute Switch", + R_ICTL0, FB_ICTL0_IN1MUTE, 1, 0), + SOC_SINGLE("Input Channel 0 Mute Switch", + R_ICTL0, FB_ICTL0_IN0MUTE, 1, 0), + SOC_SINGLE("Input Channel 1 HPF Disable Switch", + R_ICTL0, FB_ICTL0_IN1HP, 1, 0), + SOC_SINGLE("Input Channel 0 HPF Disable Switch", + R_ICTL0, FB_ICTL0_IN0HP, 1, 0), + /* R_ICTL1 PG 1 ADDR 0x0B */ + SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum), + SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum), + SOC_ENUM("Input Processor Channel 2/3 Operation", + in_proc_ch23_sel_enum), + SOC_SINGLE("Input Channel 3 Mute Switch", + R_ICTL1, FB_ICTL1_IN3MUTE, 1, 0), + SOC_SINGLE("Input Channel 2 Mute Switch", + R_ICTL1, FB_ICTL1_IN2MUTE, 1, 0), + SOC_SINGLE("Input Channel 3 HPF Disable Switch", + R_ICTL1, FB_ICTL1_IN3HP, 1, 0), + SOC_SINGLE("Input Channel 2 HPF Disable Switch", + R_ICTL1, FB_ICTL1_IN2HP, 1, 0), + /* R_MICBIAS PG 1 ADDR 0x0C */ + SOC_ENUM("Mic Bias 2 Voltage", mic_bias_2_enum), + SOC_ENUM("Mic Bias 1 Voltage", mic_bias_1_enum), + /* R_PGACTL0 PG 1 ADDR 0x0D */ + SOC_SINGLE("Input Channel 0 PGA Mute Switch", + R_PGACTL0, FB_PGACTL_PGAMUTE, 1, 0), + SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0, + FB_PGACTL_PGAVOL, + FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), + /* R_PGACTL1 PG 1 ADDR 0x0E */ + SOC_SINGLE("Input Channel 1 PGA Mute Switch", + R_PGACTL1, FB_PGACTL_PGAMUTE, 1, 0), + SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1, + FB_PGACTL_PGAVOL, + FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), + /* R_PGACTL2 PG 1 ADDR 0x0F */ + SOC_SINGLE("Input Channel 2 PGA Mute Switch", + R_PGACTL2, FB_PGACTL_PGAMUTE, 1, 0), + SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2, + FB_PGACTL_PGAVOL, + FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), + /* R_PGACTL3 PG 1 ADDR 0x10 */ + SOC_SINGLE("Input Channel 3 PGA Mute Switch", + R_PGACTL3, FB_PGACTL_PGAMUTE, 1, 0), + SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3, + FB_PGACTL_PGAVOL, + FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), + /* R_ICH0VOL PG 1 ADDR 0x12 */ + SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL, + FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), + /* R_ICH1VOL PG 1 ADDR 0x13 */ + SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL, + FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), + /* R_ICH2VOL PG 1 ADDR 0x14 */ + SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL, + FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), + /* R_ICH3VOL PG 1 ADDR 0x15 */ + SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL, + FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), + /* R_ASRCILVOL PG 1 ADDR 0x16 */ + SOC_SINGLE_TLV("ASRC Input Left Volume", R_ASRCILVOL, + FB_ASRCILVOL_ASRCILVOL, FM_ASRCILVOL_ASRCILVOL, + 0, asrc_vol_tlv_arr), + /* R_ASRCIRVOL PG 1 ADDR 0x17 */ + SOC_SINGLE_TLV("ASRC Input Right Volume", R_ASRCIRVOL, + FB_ASRCIRVOL_ASRCIRVOL, FM_ASRCIRVOL_ASRCIRVOL, + 0, asrc_vol_tlv_arr), + /* R_ASRCOLVOL PG 1 ADDR 0x18 */ + SOC_SINGLE_TLV("ASRC Output Left Volume", R_ASRCOLVOL, + FB_ASRCOLVOL_ASRCOLVOL, FM_ASRCOLVOL_ASRCOLVOL, + 0, asrc_vol_tlv_arr), + /* R_ASRCORVOL PG 1 ADDR 0x19 */ + SOC_SINGLE_TLV("ASRC Output Right Volume", R_ASRCORVOL, + FB_ASRCORVOL_ASRCOLVOL, FM_ASRCORVOL_ASRCOLVOL, + 0, asrc_vol_tlv_arr), + /* R_IVOLCTLU PG 1 ADDR 0x1C */ + /* R_ALCCTL0 PG 1 ADDR 0x1D */ + SOC_ENUM("ALC Mode", alc_mode_enum), + SOC_ENUM("ALC Reference", alc_ref_enum), + SOC_SINGLE("Input Channel 3 ALC Switch", + R_ALCCTL0, FB_ALCCTL0_ALCEN3, 1, 0), + SOC_SINGLE("Input Channel 2 ALC Switch", + R_ALCCTL0, FB_ALCCTL0_ALCEN2, 1, 0), + SOC_SINGLE("Input Channel 1 ALC Switch", + R_ALCCTL0, FB_ALCCTL0_ALCEN1, 1, 0), + SOC_SINGLE("Input Channel 0 ALC Switch", + R_ALCCTL0, FB_ALCCTL0_ALCEN0, 1, 0), + /* R_ALCCTL1 PG 1 ADDR 0x1E */ + SOC_SINGLE_TLV("ALC Max Gain Volume", R_ALCCTL1, + FB_ALCCTL1_MAXGAIN, FM_ALCCTL1_MAXGAIN, + 0, alc_max_gain_tlv_arr), + SOC_SINGLE_TLV("ALC Target Volume", R_ALCCTL1, + FB_ALCCTL1_ALCL, FM_ALCCTL1_ALCL, + 0, alc_target_tlv_arr), + /* R_ALCCTL2 PG 1 ADDR 0x1F */ + SOC_SINGLE("ALC Zero Cross Switch", + R_ALCCTL2, FB_ALCCTL2_ALCZC, 1, 0), + SOC_SINGLE_TLV("ALC Min Gain Volume", R_ALCCTL2, + FB_ALCCTL2_MINGAIN, FM_ALCCTL2_MINGAIN, + 0, alc_min_gain_tlv_arr), + SOC_SINGLE_RANGE("ALC Hold", R_ALCCTL2, + FB_ALCCTL2_HLD, 0, FM_ALCCTL2_HLD, 0), + /* R_ALCCTL3 PG 1 ADDR 0x20 */ + SOC_SINGLE_RANGE("ALC Decay", R_ALCCTL3, + FB_ALCCTL3_DCY, 0, FM_ALCCTL3_DCY, 0), + SOC_SINGLE_RANGE("ALC Attack", R_ALCCTL3, + FB_ALCCTL3_ATK, 0, FM_ALCCTL3_ATK, 0), + /* R_NGATE PG 1 ADDR 0x21 */ + SOC_SINGLE_TLV("Noise Gate Threshold Volume", R_NGATE, + FB_NGATE_NGTH, FM_NGATE_NGTH, 0, ngth_tlv_arr), + SOC_ENUM("Noise Gate Type", ngate_type_enum), + SOC_SINGLE("Noise Gate Switch", R_NGATE, FB_NGATE_NGAT, 1, 0), + /* R_DMICCTL PG 1 ADDR 0x22 */ + SOC_SINGLE("Digital Mic 2 Switch", R_DMICCTL, FB_DMICCTL_DMIC2EN, 1, 0), + SOC_SINGLE("Digital Mic 1 Switch", R_DMICCTL, FB_DMICCTL_DMIC1EN, 1, 0), + SOC_ENUM("Digital Mic Mono Select", dmic_mono_sel_enum), + /* R_DACCTL PG 2 ADDR 0x01 */ + SOC_ENUM("DAC Polarity Left", dac_pol_r_enum), + SOC_ENUM("DAC Polarity Right", dac_pol_l_enum), + SOC_ENUM("DAC Dither", dac_dith_enum), + SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0), + SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0), + /* R_SPKCTL PG 2 ADDR 0x02 */ + SOC_ENUM("Speaker Polarity Right", spk_pol_r_enum), + SOC_ENUM("Speaker Polarity Left", spk_pol_l_enum), + SOC_SINGLE("Speaker Mute Switch", R_SPKCTL, FB_SPKCTL_SPKMUTE, 1, 0), + SOC_SINGLE("Speaker De-Emphasis Switch", + R_SPKCTL, FB_SPKCTL_SPKDEM, 1, 0), + /* R_SUBCTL PG 2 ADDR 0x03 */ + SOC_ENUM("Sub Polarity", sub_pol_enum), + SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0), + SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0), + /* R_DCCTL PG 2 ADDR 0x04 */ + SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1), + SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1), + SOC_SINGLE("Speaker DC Removal Switch", + R_DCCTL, FB_DCCTL_SPKDCBYP, 1, 1), + SOC_SINGLE("DC Removal Coefficient Switch", R_DCCTL, FB_DCCTL_DCCOEFSEL, + FM_DCCTL_DCCOEFSEL, 0), + /* R_OVOLCTLU PG 2 ADDR 0x06 */ + SOC_SINGLE("Output Fade Switch", R_OVOLCTLU, FB_OVOLCTLU_OFADE, 1, 0), + /* R_MVOLL PG 2 ADDR 0x08 */ + /* R_MVOLR PG 2 ADDR 0x09 */ + SOC_DOUBLE_R_TLV("Master Volume", R_MVOLL, R_MVOLR, + FB_MVOLL_MVOL_L, FM_MVOLL_MVOL_L, 0, mvol_tlv_arr), + /* R_HPVOLL PG 2 ADDR 0x0A */ + /* R_HPVOLR PG 2 ADDR 0x0B */ + SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR, + FB_HPVOLL_HPVOL_L, FM_HPVOLL_HPVOL_L, 0, + hp_vol_tlv_arr), + /* R_SPKVOLL PG 2 ADDR 0x0C */ + /* R_SPKVOLR PG 2 ADDR 0x0D */ + SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR, + FB_SPKVOLL_SPKVOL_L, FM_SPKVOLL_SPKVOL_L, 0, + spk_vol_tlv_arr), + /* R_SUBVOL PG 2 ADDR 0x10 */ + SOC_SINGLE_TLV("Sub Volume", R_SUBVOL, + FB_SUBVOL_SUBVOL, FM_SUBVOL_SUBVOL, 0, spk_vol_tlv_arr), + /* R_SPKEQFILT PG 3 ADDR 0x01 */ + SOC_SINGLE("Speaker EQ 2 Switch", + R_SPKEQFILT, FB_SPKEQFILT_EQ2EN, 1, 0), + SOC_ENUM("Speaker EQ 2 Band", spk_eq_enums[0]), + SOC_SINGLE("Speaker EQ 1 Switch", + R_SPKEQFILT, FB_SPKEQFILT_EQ1EN, 1, 0), + SOC_ENUM("Speaker EQ 1 Band", spk_eq_enums[1]), + /* R_SPKMBCEN PG 3 ADDR 0x0A */ + SOC_SINGLE("Speaker MBC 3 Switch", + R_SPKMBCEN, FB_SPKMBCEN_MBCEN3, 1, 0), + SOC_SINGLE("Speaker MBC 2 Switch", + R_SPKMBCEN, FB_SPKMBCEN_MBCEN2, 1, 0), + SOC_SINGLE("Speaker MBC 1 Switch", + R_SPKMBCEN, FB_SPKMBCEN_MBCEN1, 1, 0), + /* R_SPKMBCCTL PG 3 ADDR 0x0B */ + SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum), + SOC_ENUM("Speaker MBC 3 Window", spk_mbc3_win_sel_enum), + SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum), + SOC_ENUM("Speaker MBC 2 Window", spk_mbc2_win_sel_enum), + SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum), + SOC_ENUM("Speaker MBC 1 Window", spk_mbc1_win_sel_enum), + /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */ + SOC_ENUM("Speaker MBC 1 Phase Polarity", spk_mbc1_phase_pol_enum), + SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1, + FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN, + 0, mbc_mug_tlv_arr), + /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */ + SOC_SINGLE_TLV("Speaker MBC 1 Compressor Threshold Volume", + R_SPKMBCTHR1, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH, + 0, thr_tlv_arr), + /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */ + SOC_ENUM("Speaker MBC 1 Compressor Ratio", spk_mbc1_comp_rat_enum), + /* R_SPKMBCATK1L PG 3 ADDR 0x0F */ + /* R_SPKMBCATK1H PG 3 ADDR 0x10 */ + SND_SOC_BYTES("Speaker MBC 1 Attack", R_SPKMBCATK1L, 2), + /* R_SPKMBCREL1L PG 3 ADDR 0x11 */ + /* R_SPKMBCREL1H PG 3 ADDR 0x12 */ + SND_SOC_BYTES("Speaker MBC 1 Release", R_SPKMBCREL1L, 2), + /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */ + SOC_ENUM("Speaker MBC 2 Phase Polarity", spk_mbc2_phase_pol_enum), + SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2, + FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN, + 0, mbc_mug_tlv_arr), + /* R_SPKMBCTHR2 PG 3 ADDR 0x14 */ + SOC_SINGLE_TLV("Speaker MBC 2 Compressor Threshold Volume", + R_SPKMBCTHR2, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH, + 0, thr_tlv_arr), + /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */ + SOC_ENUM("Speaker MBC 2 Compressor Ratio", spk_mbc2_comp_rat_enum), + /* R_SPKMBCATK2L PG 3 ADDR 0x16 */ + /* R_SPKMBCATK2H PG 3 ADDR 0x17 */ + SND_SOC_BYTES("Speaker MBC 2 Attack", R_SPKMBCATK2L, 2), + /* R_SPKMBCREL2L PG 3 ADDR 0x18 */ + /* R_SPKMBCREL2H PG 3 ADDR 0x19 */ + SND_SOC_BYTES("Speaker MBC 2 Release", R_SPKMBCREL2L, 2), + /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */ + SOC_ENUM("Speaker MBC 3 Phase Polarity", spk_mbc3_phase_pol_enum), + SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3, + FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN, + 0, mbc_mug_tlv_arr), + /* R_SPKMBCTHR3 PG 3 ADDR 0x1B */ + SOC_SINGLE_TLV("Speaker MBC 3 Threshold Volume", R_SPKMBCTHR3, + FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH, + 0, thr_tlv_arr), + /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */ + SOC_ENUM("Speaker MBC 3 Compressor Ratio", spk_mbc3_comp_rat_enum), + /* R_SPKMBCATK3L PG 3 ADDR 0x1D */ + /* R_SPKMBCATK3H PG 3 ADDR 0x1E */ + SND_SOC_BYTES("Speaker MBC 3 Attack", R_SPKMBCATK3L, 3), + /* R_SPKMBCREL3L PG 3 ADDR 0x1F */ + /* R_SPKMBCREL3H PG 3 ADDR 0x20 */ + SND_SOC_BYTES("Speaker MBC 3 Release", R_SPKMBCREL3L, 3), + /* R_SPKCLECTL PG 3 ADDR 0x21 */ + SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum), + SOC_ENUM("Speaker CLE Window", spk_cle_win_sel_enum), + SOC_SINGLE("Speaker CLE Expander Switch", + R_SPKCLECTL, FB_SPKCLECTL_EXPEN, 1, 0), + SOC_SINGLE("Speaker CLE Limiter Switch", + R_SPKCLECTL, FB_SPKCLECTL_LIMEN, 1, 0), + SOC_SINGLE("Speaker CLE Compressor Switch", + R_SPKCLECTL, FB_SPKCLECTL_COMPEN, 1, 0), + /* R_SPKCLEMUG PG 3 ADDR 0x22 */ + SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG, + FB_SPKCLEMUG_MUGAIN, FM_SPKCLEMUG_MUGAIN, + 0, cle_mug_tlv_arr), + /* R_SPKCOMPTHR PG 3 ADDR 0x23 */ + SOC_SINGLE_TLV("Speaker Compressor Threshold Volume", R_SPKCOMPTHR, + FB_SPKCOMPTHR_THRESH, FM_SPKCOMPTHR_THRESH, + 0, thr_tlv_arr), + /* R_SPKCOMPRAT PG 3 ADDR 0x24 */ + SOC_ENUM("Speaker Compressor Ratio", spk_comp_rat_enum), + /* R_SPKCOMPATKL PG 3 ADDR 0x25 */ + /* R_SPKCOMPATKH PG 3 ADDR 0x26 */ + SND_SOC_BYTES("Speaker Compressor Attack", R_SPKCOMPATKL, 2), + /* R_SPKCOMPRELL PG 3 ADDR 0x27 */ + /* R_SPKCOMPRELH PG 3 ADDR 0x28 */ + SND_SOC_BYTES("Speaker Compressor Release", R_SPKCOMPRELL, 2), + /* R_SPKLIMTHR PG 3 ADDR 0x29 */ + SOC_SINGLE_TLV("Speaker Limiter Threshold Volume", R_SPKLIMTHR, + FB_SPKLIMTHR_THRESH, FM_SPKLIMTHR_THRESH, + 0, thr_tlv_arr), + /* R_SPKLIMTGT PG 3 ADDR 0x2A */ + SOC_SINGLE_TLV("Speaker Limiter Target Volume", R_SPKLIMTGT, + FB_SPKLIMTGT_TARGET, FM_SPKLIMTGT_TARGET, + 0, thr_tlv_arr), + /* R_SPKLIMATKL PG 3 ADDR 0x2B */ + /* R_SPKLIMATKH PG 3 ADDR 0x2C */ + SND_SOC_BYTES("Speaker Limiter Attack", R_SPKLIMATKL, 2), + /* R_SPKLIMRELL PG 3 ADDR 0x2D */ + /* R_SPKLIMRELR PG 3 ADDR 0x2E */ + SND_SOC_BYTES("Speaker Limiter Release", R_SPKLIMRELL, 2), + /* R_SPKEXPTHR PG 3 ADDR 0x2F */ + SOC_SINGLE_TLV("Speaker Expander Threshold Volume", R_SPKEXPTHR, + FB_SPKEXPTHR_THRESH, FM_SPKEXPTHR_THRESH, + 0, thr_tlv_arr), + /* R_SPKEXPRAT PG 3 ADDR 0x30 */ + SOC_ENUM("Speaker Expander Ratio", spk_exp_rat_enum), + /* R_SPKEXPATKL PG 3 ADDR 0x31 */ + /* R_SPKEXPATKR PG 3 ADDR 0x32 */ + SND_SOC_BYTES("Speaker Expander Attack", R_SPKEXPATKL, 2), + /* R_SPKEXPRELL PG 3 ADDR 0x33 */ + /* R_SPKEXPRELR PG 3 ADDR 0x34 */ + SND_SOC_BYTES("Speaker Expander Release", R_SPKEXPRELL, 2), + /* R_SPKFXCTL PG 3 ADDR 0x35 */ + SOC_SINGLE("Speaker 3D Switch", R_SPKFXCTL, FB_SPKFXCTL_3DEN, 1, 0), + SOC_SINGLE("Speaker Treble Enhancement Switch", + R_SPKFXCTL, FB_SPKFXCTL_TEEN, 1, 0), + SOC_SINGLE("Speaker Treble NLF Switch", + R_SPKFXCTL, FB_SPKFXCTL_TNLFBYP, 1, 1), + SOC_SINGLE("Speaker Bass Enhancement Switch", + R_SPKFXCTL, FB_SPKFXCTL_BEEN, 1, 0), + SOC_SINGLE("Speaker Bass NLF Switch", + R_SPKFXCTL, FB_SPKFXCTL_BNLFBYP, 1, 1), + /* R_DACEQFILT PG 4 ADDR 0x01 */ + SOC_SINGLE("DAC EQ 2 Switch", + R_DACEQFILT, FB_DACEQFILT_EQ2EN, 1, 0), + SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]), + SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0), + SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]), + /* R_DACMBCEN PG 4 ADDR 0x0A */ + SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0), + SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0), + SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0), + /* R_DACMBCCTL PG 4 ADDR 0x0B */ + SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum), + SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum), + SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum), + SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum), + SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum), + SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum), + /* R_DACMBCMUG1 PG 4 ADDR 0x0C */ + SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum), + SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1, + FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN, + 0, mbc_mug_tlv_arr), + /* R_DACMBCTHR1 PG 4 ADDR 0x0D */ + SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1, + FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH, + 0, thr_tlv_arr), + /* R_DACMBCRAT1 PG 4 ADDR 0x0E */ + SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum), + /* R_DACMBCATK1L PG 4 ADDR 0x0F */ + /* R_DACMBCATK1H PG 4 ADDR 0x10 */ + SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2), + /* R_DACMBCREL1L PG 4 ADDR 0x11 */ + /* R_DACMBCREL1H PG 4 ADDR 0x12 */ + SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2), + /* R_DACMBCMUG2 PG 4 ADDR 0x13 */ + SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum), + SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2, + FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN, + 0, mbc_mug_tlv_arr), + /* R_DACMBCTHR2 PG 4 ADDR 0x14 */ + SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2, + FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH, + 0, thr_tlv_arr), + /* R_DACMBCRAT2 PG 4 ADDR 0x15 */ + SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum), + /* R_DACMBCATK2L PG 4 ADDR 0x16 */ + /* R_DACMBCATK2H PG 4 ADDR 0x17 */ + SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2), + /* R_DACMBCREL2L PG 4 ADDR 0x18 */ + /* R_DACMBCREL2H PG 4 ADDR 0x19 */ + SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2), + /* R_DACMBCMUG3 PG 4 ADDR 0x1A */ + SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum), + SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3, + FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN, + 0, mbc_mug_tlv_arr), + /* R_DACMBCTHR3 PG 4 ADDR 0x1B */ + SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3, + FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH, + 0, thr_tlv_arr), + /* R_DACMBCRAT3 PG 4 ADDR 0x1C */ + SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum), + /* R_DACMBCATK3L PG 4 ADDR 0x1D */ + /* R_DACMBCATK3H PG 4 ADDR 0x1E */ + SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3), + /* R_DACMBCREL3L PG 4 ADDR 0x1F */ + /* R_DACMBCREL3H PG 4 ADDR 0x20 */ + SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3), + /* R_DACCLECTL PG 4 ADDR 0x21 */ + SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum), + SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum), + SOC_SINGLE("DAC CLE Expander Switch", + R_DACCLECTL, FB_DACCLECTL_EXPEN, 1, 0), + SOC_SINGLE("DAC CLE Limiter Switch", + R_DACCLECTL, FB_DACCLECTL_LIMEN, 1, 0), + SOC_SINGLE("DAC CLE Compressor Switch", + R_DACCLECTL, FB_DACCLECTL_COMPEN, 1, 0), + /* R_DACCLEMUG PG 4 ADDR 0x22 */ + SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG, + FB_DACCLEMUG_MUGAIN, FM_DACCLEMUG_MUGAIN, + 0, cle_mug_tlv_arr), + /* R_DACCOMPTHR PG 4 ADDR 0x23 */ + SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR, + FB_DACCOMPTHR_THRESH, FM_DACCOMPTHR_THRESH, + 0, thr_tlv_arr), + /* R_DACCOMPRAT PG 4 ADDR 0x24 */ + SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum), + /* R_DACCOMPATKL PG 4 ADDR 0x25 */ + /* R_DACCOMPATKH PG 4 ADDR 0x26 */ + SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2), + /* R_DACCOMPRELL PG 4 ADDR 0x27 */ + /* R_DACCOMPRELH PG 4 ADDR 0x28 */ + SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2), + /* R_DACLIMTHR PG 4 ADDR 0x29 */ + SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR, + FB_DACLIMTHR_THRESH, FM_DACLIMTHR_THRESH, + 0, thr_tlv_arr), + /* R_DACLIMTGT PG 4 ADDR 0x2A */ + SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT, + FB_DACLIMTGT_TARGET, FM_DACLIMTGT_TARGET, + 0, thr_tlv_arr), + /* R_DACLIMATKL PG 4 ADDR 0x2B */ + /* R_DACLIMATKH PG 4 ADDR 0x2C */ + SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2), + /* R_DACLIMRELL PG 4 ADDR 0x2D */ + /* R_DACLIMRELR PG 4 ADDR 0x2E */ + SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2), + /* R_DACEXPTHR PG 4 ADDR 0x2F */ + SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR, + FB_DACEXPTHR_THRESH, FM_DACEXPTHR_THRESH, + 0, thr_tlv_arr), + /* R_DACEXPRAT PG 4 ADDR 0x30 */ + SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum), + /* R_DACEXPATKL PG 4 ADDR 0x31 */ + /* R_DACEXPATKR PG 4 ADDR 0x32 */ + SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2), + /* R_DACEXPRELL PG 4 ADDR 0x33 */ + /* R_DACEXPRELR PG 4 ADDR 0x34 */ + SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2), + /* R_DACFXCTL PG 4 ADDR 0x35 */ + SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0), + SOC_SINGLE("DAC Treble Enhancement Switch", + R_DACFXCTL, FB_DACFXCTL_TEEN, 1, 0), + SOC_SINGLE("DAC Treble NLF Switch", + R_DACFXCTL, FB_DACFXCTL_TNLFBYP, 1, 1), + SOC_SINGLE("DAC Bass Enhancement Switch", + R_DACFXCTL, FB_DACFXCTL_BEEN, 1, 0), + SOC_SINGLE("DAC Bass NLF Switch", + R_DACFXCTL, FB_DACFXCTL_BNLFBYP, 1, 1), + /* R_SUBEQFILT PG 5 ADDR 0x01 */ + SOC_SINGLE("Sub EQ 2 Switch", + R_SUBEQFILT, FB_SUBEQFILT_EQ2EN, 1, 0), + SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]), + SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0), + SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]), + /* R_SUBMBCEN PG 5 ADDR 0x0A */ + SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0), + SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0), + SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0), + /* R_SUBMBCCTL PG 5 ADDR 0x0B */ + SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum), + SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum), + SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum), + SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum), + SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum), + SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum), + /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */ + SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum), + SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1, + FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN, + 0, mbc_mug_tlv_arr), + /* R_SUBMBCTHR1 PG 5 ADDR 0x0D */ + SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1, + FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH, + 0, thr_tlv_arr), + /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */ + SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum), + /* R_SUBMBCATK1L PG 5 ADDR 0x0F */ + /* R_SUBMBCATK1H PG 5 ADDR 0x10 */ + SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2), + /* R_SUBMBCREL1L PG 5 ADDR 0x11 */ + /* R_SUBMBCREL1H PG 5 ADDR 0x12 */ + SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2), + /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */ + SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum), + SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2, + FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN, + 0, mbc_mug_tlv_arr), + /* R_SUBMBCTHR2 PG 5 ADDR 0x14 */ + SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2, + FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH, + 0, thr_tlv_arr), + /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */ + SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum), + /* R_SUBMBCATK2L PG 5 ADDR 0x16 */ + /* R_SUBMBCATK2H PG 5 ADDR 0x17 */ + SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2), + /* R_SUBMBCREL2L PG 5 ADDR 0x18 */ + /* R_SUBMBCREL2H PG 5 ADDR 0x19 */ + SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2), + /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */ + SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum), + SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3, + FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN, + 0, mbc_mug_tlv_arr), + /* R_SUBMBCTHR3 PG 5 ADDR 0x1B */ + SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3, + FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH, + 0, thr_tlv_arr), + /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */ + SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum), + /* R_SUBMBCATK3L PG 5 ADDR 0x1D */ + /* R_SUBMBCATK3H PG 5 ADDR 0x1E */ + SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3), + /* R_SUBMBCREL3L PG 5 ADDR 0x1F */ + /* R_SUBMBCREL3H PG 5 ADDR 0x20 */ + SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3), + /* R_SUBCLECTL PG 5 ADDR 0x21 */ + SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum), + SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum), + SOC_SINGLE("Sub CLE Expander Switch", + R_SUBCLECTL, FB_SUBCLECTL_EXPEN, 1, 0), + SOC_SINGLE("Sub CLE Limiter Switch", + R_SUBCLECTL, FB_SUBCLECTL_LIMEN, 1, 0), + SOC_SINGLE("Sub CLE Compressor Switch", + R_SUBCLECTL, FB_SUBCLECTL_COMPEN, 1, 0), + /* R_SUBCLEMUG PG 5 ADDR 0x22 */ + SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG, + FB_SUBCLEMUG_MUGAIN, FM_SUBCLEMUG_MUGAIN, + 0, cle_mug_tlv_arr), + /* R_SUBCOMPTHR PG 5 ADDR 0x23 */ + SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR, + FB_SUBCOMPTHR_THRESH, FM_SUBCOMPTHR_THRESH, + 0, thr_tlv_arr), + /* R_SUBCOMPRAT PG 5 ADDR 0x24 */ + SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum), + /* R_SUBCOMPATKL PG 5 ADDR 0x25 */ + /* R_SUBCOMPATKH PG 5 ADDR 0x26 */ + SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2), + /* R_SUBCOMPRELL PG 5 ADDR 0x27 */ + /* R_SUBCOMPRELH PG 5 ADDR 0x28 */ + SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2), + /* R_SUBLIMTHR PG 5 ADDR 0x29 */ + SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR, + FB_SUBLIMTHR_THRESH, FM_SUBLIMTHR_THRESH, + 0, thr_tlv_arr), + /* R_SUBLIMTGT PG 5 ADDR 0x2A */ + SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT, + FB_SUBLIMTGT_TARGET, FM_SUBLIMTGT_TARGET, + 0, thr_tlv_arr), + /* R_SUBLIMATKL PG 5 ADDR 0x2B */ + /* R_SUBLIMATKH PG 5 ADDR 0x2C */ + SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2), + /* R_SUBLIMRELL PG 5 ADDR 0x2D */ + /* R_SUBLIMRELR PG 5 ADDR 0x2E */ + SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2), + /* R_SUBEXPTHR PG 5 ADDR 0x2F */ + SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR, + FB_SUBEXPTHR_THRESH, FM_SUBEXPTHR_THRESH, + 0, thr_tlv_arr), + /* R_SUBEXPRAT PG 5 ADDR 0x30 */ + SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum), + /* R_SUBEXPATKL PG 5 ADDR 0x31 */ + /* R_SUBEXPATKR PG 5 ADDR 0x32 */ + SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2), + /* R_SUBEXPRELL PG 5 ADDR 0x33 */ + /* R_SUBEXPRELR PG 5 ADDR 0x34 */ + SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2), + /* R_SUBFXCTL PG 5 ADDR 0x35 */ + SOC_SINGLE("Sub Treble Enhancement Switch", + R_SUBFXCTL, FB_SUBFXCTL_TEEN, 1, 0), + SOC_SINGLE("Sub Treble NLF Switch", + R_SUBFXCTL, FB_SUBFXCTL_TNLFBYP, 1, 1), + SOC_SINGLE("Sub Bass Enhancement Switch", + R_SUBFXCTL, FB_SUBFXCTL_BEEN, 1, 0), + SOC_SINGLE("Sub Bass NLF Switch", + R_SUBFXCTL, FB_SUBFXCTL_BNLFBYP, 1, 1), + COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00), + COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05), + COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a), + COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f), + COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14), + COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19), + + COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20), + COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25), + COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a), + COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f), + COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34), + COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39), + + COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f), + COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f), + + COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40), + COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45), + COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a), + COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f), + COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54), + COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59), + + COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60), + COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65), + COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a), + COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f), + COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74), + COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79), + + COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f), + COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f), + + COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80), + COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85), + + COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a), + COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b), + + COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), + + COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), + + COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96), + + COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97), + COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c), + + COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1), + COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2), + + COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), + + COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), + + COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad), + + COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae), + + COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf), + + COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0), + COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5), + + COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba), + COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf), + + COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4), + COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9), + + COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00), + COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05), + COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a), + COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f), + COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14), + COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19), + + COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20), + COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25), + COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a), + COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f), + COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34), + COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39), + + COEFF_RAM_CTL("Speaker Cascade 1 Left Prescale", COEFF_SIZE, 0x1f), + COEFF_RAM_CTL("Speaker Cascade 1 Right Prescale", COEFF_SIZE, 0x3f), + + COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40), + COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45), + COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a), + COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f), + COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54), + COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59), + + COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60), + COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65), + COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a), + COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f), + COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74), + COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79), + + COEFF_RAM_CTL("Speaker Cascade 2 Left Prescale", COEFF_SIZE, 0x5f), + COEFF_RAM_CTL("Speaker Cascade 2 Right Prescale", COEFF_SIZE, 0x7f), + + COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80), + COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85), + + COEFF_RAM_CTL("Speaker Bass Non Linear Function 1", COEFF_SIZE, 0x8a), + COEFF_RAM_CTL("Speaker Bass Non Linear Function 2", COEFF_SIZE, 0x8b), + + COEFF_RAM_CTL("Speaker Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), + + COEFF_RAM_CTL("Speaker Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), + + COEFF_RAM_CTL("Speaker Bass Mix", COEFF_SIZE, 0x96), + + COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97), + COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c), + + COEFF_RAM_CTL("Speaker Treb Non Linear Function 1", COEFF_SIZE, 0xa1), + COEFF_RAM_CTL("Speaker Treb Non Linear Function 2", COEFF_SIZE, 0xa2), + + COEFF_RAM_CTL("Speaker Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), + + COEFF_RAM_CTL("Speaker Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), + + COEFF_RAM_CTL("Speaker Treb Mix", COEFF_SIZE, 0xad), + + COEFF_RAM_CTL("Speaker 3D", COEFF_SIZE, 0xae), + + COEFF_RAM_CTL("Speaker 3D Mix", COEFF_SIZE, 0xaf), + + COEFF_RAM_CTL("Speaker MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0), + COEFF_RAM_CTL("Speaker MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5), + + COEFF_RAM_CTL("Speaker MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba), + COEFF_RAM_CTL("Speaker MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf), + + COEFF_RAM_CTL("Speaker MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4), + COEFF_RAM_CTL("Speaker MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9), + + COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00), + COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05), + COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a), + COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f), + COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14), + COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19), + + COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20), + COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25), + COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a), + COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f), + COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34), + COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39), + + COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f), + COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f), + + COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40), + COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45), + COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a), + COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f), + COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54), + COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59), + + COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60), + COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65), + COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a), + COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f), + COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74), + COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79), + + COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f), + COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f), + + COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80), + COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85), + + COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a), + COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b), + + COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), + + COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), + + COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96), + + COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97), + COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c), + + COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1), + COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2), + + COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), + + COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), + + COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad), + + COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae), + + COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf), + + COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0), + COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5), + + COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba), + COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf), + + COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4), + COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9), +}; + +static struct snd_soc_dapm_widget const tscs454_dapm_widgets[] = { + /* R_PLLCTL PG 0 ADDR 0x15 */ + SND_SOC_DAPM_SUPPLY("PLL 1 Power", R_PLLCTL, FB_PLLCTL_PU_PLL1, 0, + pll_power_event, + SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_SUPPLY("PLL 2 Power", R_PLLCTL, FB_PLLCTL_PU_PLL2, 0, + pll_power_event, + SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), + /* R_I2SPINC0 PG 0 ADDR 0x22 */ + SND_SOC_DAPM_AIF_OUT("DAI 3 Out", "DAI 3 Capture", 0, + R_I2SPINC0, FB_I2SPINC0_SDO3TRI, 1), + SND_SOC_DAPM_AIF_OUT("DAI 2 Out", "DAI 2 Capture", 0, + R_I2SPINC0, FB_I2SPINC0_SDO2TRI, 1), + SND_SOC_DAPM_AIF_OUT("DAI 1 Out", "DAI 1 Capture", 0, + R_I2SPINC0, FB_I2SPINC0_SDO1TRI, 1), + /* R_PWRM0 PG 0 ADDR 0x33 */ + SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL, + R_PWRM0, FB_PWRM0_INPROC3PU, 0), + SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL, + R_PWRM0, FB_PWRM0_INPROC2PU, 0), + SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL, + R_PWRM0, FB_PWRM0_INPROC1PU, 0), + SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL, + R_PWRM0, FB_PWRM0_INPROC0PU, 0), + SND_SOC_DAPM_SUPPLY("Mic Bias 2", + R_PWRM0, FB_PWRM0_MICB2PU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Mic Bias 1", R_PWRM0, + FB_PWRM0_MICB1PU, 0, NULL, 0), + /* R_PWRM1 PG 0 ADDR 0x34 */ + SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Headphone Left Power", + R_PWRM1, FB_PWRM1_HPLPU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Headphone Right Power", + R_PWRM1, FB_PWRM1_HPRPU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Speaker Left Power", + R_PWRM1, FB_PWRM1_SPKLPU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Speaker Right Power", + R_PWRM1, FB_PWRM1_SPKRPU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Differential Input 2 Power", + R_PWRM1, FB_PWRM1_D2S2PU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Differential Input 1 Power", + R_PWRM1, FB_PWRM1_D2S1PU, 0, NULL, 0), + /* R_PWRM2 PG 0 ADDR 0x35 */ + SND_SOC_DAPM_SUPPLY("DAI 3 Out Power", + R_PWRM2, FB_PWRM2_I2S3OPU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAI 2 Out Power", + R_PWRM2, FB_PWRM2_I2S2OPU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAI 1 Out Power", + R_PWRM2, FB_PWRM2_I2S1OPU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAI 3 In Power", + R_PWRM2, FB_PWRM2_I2S3IPU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAI 2 In Power", + R_PWRM2, FB_PWRM2_I2S2IPU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAI 1 In Power", + R_PWRM2, FB_PWRM2_I2S1IPU, 0, NULL, 0), + /* R_PWRM3 PG 0 ADDR 0x36 */ + SND_SOC_DAPM_SUPPLY("Line Out Left Power", + R_PWRM3, FB_PWRM3_LLINEPU, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Line Out Right Power", + R_PWRM3, FB_PWRM3_RLINEPU, 0, NULL, 0), + /* R_PWRM4 PG 0 ADDR 0x37 */ + SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0), + SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0), + SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0), + SND_SOC_DAPM_DAC("ClassD Left", NULL, R_PWRM4, FB_PWRM4_OPSPKLPU, 0), + SND_SOC_DAPM_DAC("ClassD Right", NULL, R_PWRM4, FB_PWRM4_OPSPKRPU, 0), + /* R_AUDIOMUX1 PG 0 ADDR 0x3A */ + SND_SOC_DAPM_MUX("DAI 2 Out Mux", SND_SOC_NOPM, 0, 0, + &dai2_mux_dapm_enum), + SND_SOC_DAPM_MUX("DAI 1 Out Mux", SND_SOC_NOPM, 0, 0, + &dai1_mux_dapm_enum), + /* R_AUDIOMUX2 PG 0 ADDR 0x3B */ + SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0, + &dac_mux_dapm_enum), + SND_SOC_DAPM_MUX("DAI 3 Out Mux", SND_SOC_NOPM, 0, 0, + &dai3_mux_dapm_enum), + /* R_AUDIOMUX3 PG 0 ADDR 0x3C */ + SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0, + &sub_mux_dapm_enum), + SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0, + &classd_mux_dapm_enum), + /* R_HSDCTL1 PG 1 ADDR 0x01 */ + SND_SOC_DAPM_SUPPLY("GHS Detect Power", R_HSDCTL1, + FB_HSDCTL1_CON_DET_PWD, 1, NULL, 0), + /* R_CH0AIC PG 1 ADDR 0x06 */ + SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0, + &in_bst_mux_ch0_dapm_enum), + SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0, + &adc_mux_ch0_dapm_enum), + SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0, + &in_proc_mux_ch0_dapm_enum), + /* R_CH1AIC PG 1 ADDR 0x07 */ + SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0, + &in_bst_mux_ch1_dapm_enum), + SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0, + &adc_mux_ch1_dapm_enum), + SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0, + &in_proc_mux_ch1_dapm_enum), + /* Virtual */ + SND_SOC_DAPM_AIF_IN("DAI 3 In", "DAI 3 Playback", 0, + SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("DAI 2 In", "DAI 2 Playback", 0, + SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("DAI 1 In", "DAI 1 Playback", 0, + SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_SUPPLY("PLLs", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_OUTPUT("Sub Out"), + SND_SOC_DAPM_OUTPUT("Headphone Left"), + SND_SOC_DAPM_OUTPUT("Headphone Right"), + SND_SOC_DAPM_OUTPUT("Speaker Left"), + SND_SOC_DAPM_OUTPUT("Speaker Right"), + SND_SOC_DAPM_OUTPUT("Line Out Left"), + SND_SOC_DAPM_OUTPUT("Line Out Right"), + SND_SOC_DAPM_INPUT("D2S 2"), + SND_SOC_DAPM_INPUT("D2S 1"), + SND_SOC_DAPM_INPUT("Line In 1 Left"), + SND_SOC_DAPM_INPUT("Line In 1 Right"), + SND_SOC_DAPM_INPUT("Line In 2 Left"), + SND_SOC_DAPM_INPUT("Line In 2 Right"), + SND_SOC_DAPM_INPUT("Line In 3 Left"), + SND_SOC_DAPM_INPUT("Line In 3 Right"), + SND_SOC_DAPM_INPUT("DMic 1"), + SND_SOC_DAPM_INPUT("DMic 2"), + + SND_SOC_DAPM_MUX("CH 0_1 Mux", SND_SOC_NOPM, 0, 0, + &ch_0_1_mux_dapm_enum), + SND_SOC_DAPM_MUX("CH 2_3 Mux", SND_SOC_NOPM, 0, 0, + &ch_2_3_mux_dapm_enum), + SND_SOC_DAPM_MUX("CH 4_5 Mux", SND_SOC_NOPM, 0, 0, + &ch_4_5_mux_dapm_enum), +}; + +static struct snd_soc_dapm_route const tscs454_intercon[] = { + /* PLLs */ + {"PLLs", NULL, "PLL 1 Power", pll_connected}, + {"PLLs", NULL, "PLL 2 Power", pll_connected}, + /* Inputs */ + {"DAI 3 In", NULL, "DAI 3 In Power"}, + {"DAI 2 In", NULL, "DAI 2 In Power"}, + {"DAI 1 In", NULL, "DAI 1 In Power"}, + /* Outputs */ + {"DAI 3 Out", NULL, "DAI 3 Out Power"}, + {"DAI 2 Out", NULL, "DAI 2 Out Power"}, + {"DAI 1 Out", NULL, "DAI 1 Out Power"}, + /* Ch Muxing */ + {"CH 0_1 Mux", "DAI 1", "DAI 1 In"}, + {"CH 0_1 Mux", "TDM 0_1", "DAI 1 In"}, + {"CH 2_3 Mux", "DAI 2", "DAI 2 In"}, + {"CH 2_3 Mux", "TDM 2_3", "DAI 1 In"}, + {"CH 4_5 Mux", "DAI 3", "DAI 2 In"}, + {"CH 4_5 Mux", "TDM 4_5", "DAI 1 In"}, + /* In/Out Muxing */ + {"DAI 1 Out Mux", "CH 0_1", "CH 0_1 Mux"}, + {"DAI 1 Out Mux", "CH 2_3", "CH 2_3 Mux"}, + {"DAI 1 Out Mux", "CH 4_5", "CH 4_5 Mux"}, + {"DAI 2 Out Mux", "CH 0_1", "CH 0_1 Mux"}, + {"DAI 2 Out Mux", "CH 2_3", "CH 2_3 Mux"}, + {"DAI 2 Out Mux", "CH 4_5", "CH 4_5 Mux"}, + {"DAI 3 Out Mux", "CH 0_1", "CH 0_1 Mux"}, + {"DAI 3 Out Mux", "CH 2_3", "CH 2_3 Mux"}, + {"DAI 3 Out Mux", "CH 4_5", "CH 4_5 Mux"}, + /****************** + * Playback Paths * + ******************/ + /* DAC Path */ + {"DAC Mux", "CH 4_5", "CH 4_5 Mux"}, + {"DAC Mux", "CH 2_3", "CH 2_3 Mux"}, + {"DAC Mux", "CH 0_1", "CH 0_1 Mux"}, + {"DAC Left", NULL, "DAC Mux"}, + {"DAC Right", NULL, "DAC Mux"}, + {"DAC Left", NULL, "PLLs"}, + {"DAC Right", NULL, "PLLs"}, + {"Headphone Left", NULL, "Headphone Left Power"}, + {"Headphone Right", NULL, "Headphone Right Power"}, + {"Headphone Left", NULL, "DAC Left"}, + {"Headphone Right", NULL, "DAC Right"}, + /* Line Out */ + {"Line Out Left", NULL, "Line Out Left Power"}, + {"Line Out Right", NULL, "Line Out Right Power"}, + {"Line Out Left", NULL, "DAC Left"}, + {"Line Out Right", NULL, "DAC Right"}, + /* ClassD Path */ + {"Speaker Mux", "CH 4_5", "CH 4_5 Mux"}, + {"Speaker Mux", "CH 2_3", "CH 2_3 Mux"}, + {"Speaker Mux", "CH 0_1", "CH 0_1 Mux"}, + {"ClassD Left", NULL, "Speaker Mux"}, + {"ClassD Right", NULL, "Speaker Mux"}, + {"ClassD Left", NULL, "PLLs"}, + {"ClassD Right", NULL, "PLLs"}, + {"Speaker Left", NULL, "Speaker Left Power"}, + {"Speaker Right", NULL, "Speaker Right Power"}, + {"Speaker Left", NULL, "ClassD Left"}, + {"Speaker Right", NULL, "ClassD Right"}, + /* Sub Path */ + {"Sub Mux", "CH 4", "CH 4_5 Mux"}, + {"Sub Mux", "CH 5", "CH 4_5 Mux"}, + {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"}, + {"Sub Mux", "CH 2", "CH 2_3 Mux"}, + {"Sub Mux", "CH 3", "CH 2_3 Mux"}, + {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"}, + {"Sub Mux", "CH 0", "CH 0_1 Mux"}, + {"Sub Mux", "CH 1", "CH 0_1 Mux"}, + {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"}, + {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"}, + {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"}, + {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"}, + {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"}, + {"Sub Mux", "DMic 2 Left", "DMic 2"}, + {"Sub Mux", "DMic 2 Right", "DMic 2"}, + {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"}, + {"Sub Mux", "ClassD Left", "ClassD Left"}, + {"Sub Mux", "ClassD Right", "ClassD Right"}, + {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"}, + {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"}, + {"Sub", NULL, "Sub Mux"}, + {"Sub", NULL, "PLLs"}, + {"Sub Out", NULL, "Sub Power"}, + {"Sub Out", NULL, "Sub"}, + /***************** + * Capture Paths * + *****************/ + {"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"}, + {"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"}, + {"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"}, + {"Input Boost Channel 0 Mux", "D2S", "D2S 1"}, + + {"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"}, + {"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"}, + {"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"}, + {"Input Boost Channel 1 Mux", "D2S", "D2S 2"}, + + {"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"}, + {"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"}, + {"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"}, + {"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"}, + + {"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"}, + {"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"}, + {"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"}, + {"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"}, + + {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"}, + {"Input Processor Channel 0 Mux", "DMic", "DMic 1"}, + + {"Input Processor Channel 0", NULL, "PLLs"}, + {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"}, + + {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"}, + {"Input Processor Channel 1 Mux", "DMic", "DMic 1"}, + + {"Input Processor Channel 1", NULL, "PLLs"}, + {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"}, + + {"Input Processor Channel 2", NULL, "PLLs"}, + {"Input Processor Channel 2", NULL, "DMic 2"}, + + {"Input Processor Channel 3", NULL, "PLLs"}, + {"Input Processor Channel 3", NULL, "DMic 2"}, + + {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"}, + {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"}, + {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"}, + {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"}, + + {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"}, + {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"}, + {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"}, + {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"}, + + {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"}, + {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"}, + {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"}, + {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"}, + + {"DAI 1 Out", NULL, "DAI 1 Out Mux"}, + {"DAI 2 Out", NULL, "DAI 2 Out Mux"}, + {"DAI 3 Out", NULL, "DAI 3 Out Mux"}, +}; + +/* This is used when BCLK is sourcing the PLLs */ +static int tscs454_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_component *component = dai->component; + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + unsigned int val; + int bclk_dai; + int ret; + + dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq); + + ret = snd_soc_component_read(component, R_PLLCTL, &val); + if (ret < 0) + return ret; + + bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL; + if (bclk_dai != dai->id) + return 0; + + tscs454->bclk_freq = freq; + return set_sysclk(component); +} + +static int tscs454_set_bclk_ratio(struct snd_soc_dai *dai, + unsigned int ratio) +{ + unsigned int mask; + int ret; + struct snd_soc_component *component = dai->component; + unsigned int val; + int shift; + + dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n", + dai->id, ratio); + + switch (dai->id) { + case TSCS454_DAI1_ID: + mask = FM_I2SCMC_BCMP1; + shift = FB_I2SCMC_BCMP1; + break; + case TSCS454_DAI2_ID: + mask = FM_I2SCMC_BCMP2; + shift = FB_I2SCMC_BCMP2; + break; + case TSCS454_DAI3_ID: + mask = FM_I2SCMC_BCMP3; + shift = FB_I2SCMC_BCMP3; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Unknown audio interface (%d)\n", ret); + return ret; + } + + switch (ratio) { + case 32: + val = I2SCMC_BCMP_32X; + break; + case 40: + val = I2SCMC_BCMP_40X; + break; + case 64: + val = I2SCMC_BCMP_64X; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret); + return ret; + } + + ret = snd_soc_component_update_bits(component, + R_I2SCMC, mask, val << shift); + if (ret < 0) { + dev_err(component->dev, + "Failed to set DAI BCLK ratio (%d)\n", ret); + return ret; + } + + return 0; +} + +static inline int set_aif_master_from_fmt(struct snd_soc_component *component, + struct aif *aif, unsigned int fmt) +{ + int ret; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + aif->master = true; + break; + case SND_SOC_DAIFMT_CBS_CFS: + aif->master = false; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Unsupported format (%d)\n", ret); + return ret; + } + + return 0; +} + +static inline int set_aif_tdm_delay(struct snd_soc_component *component, + unsigned int dai_id, bool delay) +{ + unsigned int reg; + int ret; + + switch (dai_id) { + case TSCS454_DAI1_ID: + reg = R_TDMCTL0; + break; + case TSCS454_DAI2_ID: + reg = R_PCMP2CTL0; + break; + case TSCS454_DAI3_ID: + reg = R_PCMP3CTL0; + break; + default: + ret = -EINVAL; + dev_err(component->dev, + "DAI %d unknown (%d)\n", dai_id + 1, ret); + return ret; + } + ret = snd_soc_component_update_bits(component, + reg, FM_TDMCTL0_BDELAY, delay); + if (ret < 0) { + dev_err(component->dev, "Failed to setup tdm format (%d)\n", + ret); + return ret; + } + + return 0; +} + +static inline int set_aif_format_from_fmt(struct snd_soc_component *component, + unsigned int dai_id, unsigned int fmt) +{ + unsigned int reg; + unsigned int val; + int ret; + + switch (dai_id) { + case TSCS454_DAI1_ID: + reg = R_I2SP1CTL; + break; + case TSCS454_DAI2_ID: + reg = R_I2SP2CTL; + break; + case TSCS454_DAI3_ID: + reg = R_I2SP3CTL; + break; + default: + ret = -EINVAL; + dev_err(component->dev, + "DAI %d unknown (%d)\n", dai_id + 1, ret); + return ret; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_RIGHT_J: + val = FV_FORMAT_RIGHT; + break; + case SND_SOC_DAIFMT_LEFT_J: + val = FV_FORMAT_LEFT; + break; + case SND_SOC_DAIFMT_I2S: + val = FV_FORMAT_I2S; + break; + case SND_SOC_DAIFMT_DSP_A: + ret = set_aif_tdm_delay(component, dai_id, true); + if (ret < 0) + return ret; + val = FV_FORMAT_TDM; + break; + case SND_SOC_DAIFMT_DSP_B: + ret = set_aif_tdm_delay(component, dai_id, false); + if (ret < 0) + return ret; + val = FV_FORMAT_TDM; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Format unsupported (%d)\n", ret); + return ret; + } + + ret = snd_soc_component_update_bits(component, + reg, FM_I2SPCTL_FORMAT, val); + if (ret < 0) { + dev_err(component->dev, "Failed to set DAI %d format (%d)\n", + dai_id + 1, ret); + return ret; + } + + return 0; +} + +static inline int +set_aif_clock_format_from_fmt(struct snd_soc_component *component, + unsigned int dai_id, unsigned int fmt) +{ + unsigned int reg; + unsigned int val; + int ret; + + switch (dai_id) { + case TSCS454_DAI1_ID: + reg = R_I2SP1CTL; + break; + case TSCS454_DAI2_ID: + reg = R_I2SP2CTL; + break; + case TSCS454_DAI3_ID: + reg = R_I2SP3CTL; + break; + default: + ret = -EINVAL; + dev_err(component->dev, + "DAI %d unknown (%d)\n", dai_id + 1, ret); + return ret; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED; + break; + case SND_SOC_DAIFMT_NB_IF: + val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED; + break; + case SND_SOC_DAIFMT_IB_NF: + val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED; + break; + case SND_SOC_DAIFMT_IB_IF: + val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Format unknown (%d)\n", ret); + return ret; + } + + ret = snd_soc_component_update_bits(component, reg, + FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val); + if (ret < 0) { + dev_err(component->dev, + "Failed to set clock polarity for DAI%d (%d)\n", + dai_id + 1, ret); + return ret; + } + + return 0; +} + +static int tscs454_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_component *component = dai->component; + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + struct aif *aif = &tscs454->aifs[dai->id]; + int ret; + + ret = set_aif_master_from_fmt(component, aif, fmt); + if (ret < 0) + return ret; + + ret = set_aif_format_from_fmt(component, dai->id, fmt); + if (ret < 0) + return ret; + + ret = set_aif_clock_format_from_fmt(component, dai->id, fmt); + if (ret < 0) + return ret; + + return 0; +} + +static int tscs454_dai1_set_tdm_slot(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, int slots, + int slot_width) +{ + struct snd_soc_component *component = dai->component; + unsigned int val; + int ret; + + if (!slots) + return 0; + + if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) { + ret = -EINVAL; + dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); + return ret; + } + + switch (slots) { + case 2: + val = FV_TDMSO_2 | FV_TDMSI_2; + break; + case 4: + val = FV_TDMSO_4 | FV_TDMSI_4; + break; + case 6: + val = FV_TDMSO_6 | FV_TDMSI_6; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Invalid number of slots (%d)\n", ret); + return ret; + } + + switch (slot_width) { + case 16: + val = val | FV_TDMDSS_16; + break; + case 24: + val = val | FV_TDMDSS_24; + break; + case 32: + val = val | FV_TDMDSS_32; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); + return ret; + } + ret = snd_soc_component_write(component, R_TDMCTL1, val); + if (ret < 0) { + dev_err(component->dev, "Failed to set slots (%d)\n", ret); + return ret; + } + + return 0; +} + +static int tscs454_dai23_set_tdm_slot(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, int slots, + int slot_width) +{ + struct snd_soc_component *component = dai->component; + unsigned int reg; + unsigned int val; + int ret; + + if (!slots) + return 0; + + if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) { + ret = -EINVAL; + dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); + return ret; + } + + switch (dai->id) { + case TSCS454_DAI2_ID: + reg = R_PCMP2CTL1; + break; + case TSCS454_DAI3_ID: + reg = R_PCMP3CTL1; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Unrecognized interface %d (%d)\n", + dai->id, ret); + return ret; + } + + switch (slots) { + case 1: + val = FV_PCMSOP_1 | FV_PCMSIP_1; + break; + case 2: + val = FV_PCMSOP_2 | FV_PCMSIP_2; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Invalid number of slots (%d)\n", ret); + return ret; + } + + switch (slot_width) { + case 16: + val = val | FV_PCMDSSP_16; + break; + case 24: + val = val | FV_PCMDSSP_24; + break; + case 32: + val = val | FV_PCMDSSP_32; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); + return ret; + } + ret = snd_soc_component_write(component, reg, val); + if (ret < 0) { + dev_err(component->dev, "Failed to set slots (%d)\n", ret); + return ret; + } + + return 0; +} + +static int set_aif_fs(struct snd_soc_component *component, + unsigned int id, + unsigned int rate) +{ + unsigned int reg; + unsigned int br; + unsigned int bm; + int ret; + + switch (rate) { + case 8000: + br = FV_I2SMBR_32; + bm = FV_I2SMBM_0PT25; + break; + case 16000: + br = FV_I2SMBR_32; + bm = FV_I2SMBM_0PT5; + break; + case 24000: + br = FV_I2SMBR_48; + bm = FV_I2SMBM_0PT5; + break; + case 32000: + br = FV_I2SMBR_32; + bm = FV_I2SMBM_1; + break; + case 48000: + br = FV_I2SMBR_48; + bm = FV_I2SMBM_1; + break; + case 96000: + br = FV_I2SMBR_48; + bm = FV_I2SMBM_2; + break; + case 11025: + br = FV_I2SMBR_44PT1; + bm = FV_I2SMBM_0PT25; + break; + case 22050: + br = FV_I2SMBR_44PT1; + bm = FV_I2SMBM_0PT5; + break; + case 44100: + br = FV_I2SMBR_44PT1; + bm = FV_I2SMBM_1; + break; + case 88200: + br = FV_I2SMBR_44PT1; + bm = FV_I2SMBM_2; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Unsupported sample rate (%d)\n", ret); + return ret; + } + + switch (id) { + case TSCS454_DAI1_ID: + reg = R_I2S1MRATE; + break; + case TSCS454_DAI2_ID: + reg = R_I2S2MRATE; + break; + case TSCS454_DAI3_ID: + reg = R_I2S3MRATE; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "DAI ID not recognized (%d)\n", ret); + return ret; + } + + ret = snd_soc_component_update_bits(component, reg, + FM_I2SMRATE_I2SMBR | FM_I2SMRATE_I2SMBM, br|bm); + if (ret < 0) { + dev_err(component->dev, + "Failed to update register (%d)\n", ret); + return ret; + } + + return 0; +} + +static int set_aif_sample_format(struct snd_soc_component *component, + snd_pcm_format_t format, + int aif_id) +{ + unsigned int reg; + unsigned int width; + int ret; + + switch (format) { + case SNDRV_PCM_FORMAT_S16_LE: + width = FV_WL_16; + break; + case SNDRV_PCM_FORMAT_S20_3LE: + width = FV_WL_20; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + width = FV_WL_24; + break; + case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S32_LE: + width = FV_WL_32; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Unsupported format width (%d)\n", ret); + return ret; + } + + switch (aif_id) { + case TSCS454_DAI1_ID: + reg = R_I2SP1CTL; + break; + case TSCS454_DAI2_ID: + reg = R_I2SP2CTL; + break; + case TSCS454_DAI3_ID: + reg = R_I2SP3CTL; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "AIF ID not recognized (%d)\n", ret); + return ret; + } + + ret = snd_soc_component_update_bits(component, + reg, FM_I2SPCTL_WL, width); + if (ret < 0) { + dev_err(component->dev, + "Failed to set sample width (%d)\n", ret); + return ret; + } + + return 0; +} + +static int tscs454_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + unsigned int fs = params_rate(params); + struct aif *aif = &tscs454->aifs[dai->id]; + unsigned int val; + int ret; + + mutex_lock(&tscs454->aifs_status_lock); + + dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__, + aif->id, fs); + + if (!aif_active(&tscs454->aifs_status, aif->id)) { + if (PLL_44_1K_RATE % fs) + aif->pll = &tscs454->pll1; + else + aif->pll = &tscs454->pll2; + + dev_dbg(component->dev, "Reserving pll %d for aif %d\n", + aif->pll->id, aif->id); + + reserve_pll(aif->pll); + } + + if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */ + ret = snd_soc_component_read(component, R_ISRC, &val); + if (ret < 0) + goto exit; + + if ((val & FM_ISRC_IBR) == FV_IBR_48) + tscs454->internal_rate.pll = &tscs454->pll1; + else + tscs454->internal_rate.pll = &tscs454->pll2; + + dev_dbg(component->dev, "Reserving pll %d for ir\n", + tscs454->internal_rate.pll->id); + + reserve_pll(tscs454->internal_rate.pll); + } + + ret = set_aif_fs(component, aif->id, fs); + if (ret < 0) { + dev_err(component->dev, "Failed to set aif fs (%d)\n", ret); + goto exit; + } + + ret = set_aif_sample_format(component, params_format(params), aif->id); + if (ret < 0) { + dev_err(component->dev, + "Failed to set aif sample format (%d)\n", ret); + goto exit; + } + + set_aif_status_active(&tscs454->aifs_status, aif->id, + substream->stream == SNDRV_PCM_STREAM_PLAYBACK); + + dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n", + aif->id, tscs454->aifs_status.streams); + + ret = 0; +exit: + mutex_unlock(&tscs454->aifs_status_lock); + + return ret; +} + +static int tscs454_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + struct aif *aif = &tscs454->aifs[dai->id]; + + return aif_free(component, aif, + substream->stream == SNDRV_PCM_STREAM_PLAYBACK); +} + +static int tscs454_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int ret; + struct snd_soc_component *component = dai->component; + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + struct aif *aif = &tscs454->aifs[dai->id]; + + ret = aif_prepare(component, aif); + if (ret < 0) + return ret; + + return 0; +} + +static struct snd_soc_dai_ops const tscs454_dai1_ops = { + .set_sysclk = tscs454_set_sysclk, + .set_bclk_ratio = tscs454_set_bclk_ratio, + .set_fmt = tscs454_set_dai_fmt, + .set_tdm_slot = tscs454_dai1_set_tdm_slot, + .hw_params = tscs454_hw_params, + .hw_free = tscs454_hw_free, + .prepare = tscs454_prepare, +}; + +static struct snd_soc_dai_ops const tscs454_dai23_ops = { + .set_sysclk = tscs454_set_sysclk, + .set_bclk_ratio = tscs454_set_bclk_ratio, + .set_fmt = tscs454_set_dai_fmt, + .set_tdm_slot = tscs454_dai23_set_tdm_slot, + .hw_params = tscs454_hw_params, + .hw_free = tscs454_hw_free, + .prepare = tscs454_prepare, +}; + +static int tscs454_probe(struct snd_soc_component *component) +{ + struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); + unsigned int val; + int ret = 0; + + switch (tscs454->sysclk_src_id) { + case PLL_INPUT_XTAL: + val = FV_PLLISEL_XTAL; + break; + case PLL_INPUT_MCLK1: + val = FV_PLLISEL_MCLK1; + break; + case PLL_INPUT_MCLK2: + val = FV_PLLISEL_MCLK2; + break; + case PLL_INPUT_BCLK: + val = FV_PLLISEL_BCLK; + break; + default: + ret = -EINVAL; + dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret); + return ret; + } + + ret = snd_soc_component_update_bits(component, R_PLLCTL, + FM_PLLCTL_PLLISEL, val); + if (ret < 0) { + dev_err(component->dev, "Failed to set PLL input (%d)\n", ret); + return ret; + } + + if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) + ret = set_sysclk(component); + + return ret; +} + +static const struct snd_soc_component_driver soc_component_dev_tscs454 = { + .probe = tscs454_probe, + .dapm_widgets = tscs454_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(tscs454_dapm_widgets), + .dapm_routes = tscs454_intercon, + .num_dapm_routes = ARRAY_SIZE(tscs454_intercon), + .controls = tscs454_snd_controls, + .num_controls = ARRAY_SIZE(tscs454_snd_controls), +}; + +#define TSCS454_RATES SNDRV_PCM_RATE_8000_96000 + +#define TSCS454_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ + | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \ + | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver tscs454_dais[] = { + { + .name = "tscs454-dai1", + .id = TSCS454_DAI1_ID, + .playback = { + .stream_name = "DAI 1 Playback", + .channels_min = 1, + .channels_max = 6, + .rates = TSCS454_RATES, + .formats = TSCS454_FORMATS,}, + .capture = { + .stream_name = "DAI 1 Capture", + .channels_min = 1, + .channels_max = 6, + .rates = TSCS454_RATES, + .formats = TSCS454_FORMATS,}, + .ops = &tscs454_dai1_ops, + .symmetric_rates = 1, + .symmetric_channels = 1, + .symmetric_samplebits = 1, + }, + { + .name = "tscs454-dai2", + .id = TSCS454_DAI2_ID, + .playback = { + .stream_name = "DAI 2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = TSCS454_RATES, + .formats = TSCS454_FORMATS,}, + .capture = { + .stream_name = "DAI 2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = TSCS454_RATES, + .formats = TSCS454_FORMATS,}, + .ops = &tscs454_dai23_ops, + .symmetric_rates = 1, + .symmetric_channels = 1, + .symmetric_samplebits = 1, + }, + { + .name = "tscs454-dai3", + .id = TSCS454_DAI3_ID, + .playback = { + .stream_name = "DAI 3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = TSCS454_RATES, + .formats = TSCS454_FORMATS,}, + .capture = { + .stream_name = "DAI 3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = TSCS454_RATES, + .formats = TSCS454_FORMATS,}, + .ops = &tscs454_dai23_ops, + .symmetric_rates = 1, + .symmetric_channels = 1, + .symmetric_samplebits = 1, + }, +}; + +static char const * const src_names[] = { + "xtal", "mclk1", "mclk2", "bclk"}; + +static int tscs454_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct tscs454 *tscs454; + int src; + int ret; + + tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL); + if (!tscs454) + return -ENOMEM; + + ret = tscs454_data_init(tscs454, i2c); + if (ret < 0) + return ret; + + i2c_set_clientdata(i2c, tscs454); + + for (src = PLL_INPUT_XTAL; src < PLL_INPUT_BCLK; src++) { + tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]); + if (!IS_ERR(tscs454->sysclk)) { + break; + } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) { + ret = PTR_ERR(tscs454->sysclk); + dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret); + return ret; + } + } + dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]); + tscs454->sysclk_src_id = src; + + ret = regmap_write(tscs454->regmap, + R_RESET, FV_RESET_PWR_ON_DEFAULTS); + if (ret < 0) { + dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret); + return ret; + } + regcache_mark_dirty(tscs454->regmap); + + ret = regmap_register_patch(tscs454->regmap, tscs454_patch, + ARRAY_SIZE(tscs454_patch)); + if (ret < 0) { + dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret); + return ret; + } + /* Sync pg sel reg with cache */ + regmap_write(tscs454->regmap, R_PAGESEL, 0x00); + + ret = snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454, + tscs454_dais, ARRAY_SIZE(tscs454_dais)); + if (ret) { + dev_err(&i2c->dev, "Failed to register component (%d)\n", ret); + return ret; + } + + return 0; +} + +static const struct i2c_device_id tscs454_i2c_id[] = { + { "tscs454", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, tscs454_i2c_id); + +static const struct of_device_id tscs454_of_match[] = { + { .compatible = "tempo,tscs454", }, + { } +}; +MODULE_DEVICE_TABLE(of, tscs454_of_match); + +static struct i2c_driver tscs454_i2c_driver = { + .driver = { + .name = "tscs454", + .of_match_table = tscs454_of_match, + }, + .probe = tscs454_i2c_probe, + .id_table = tscs454_i2c_id, +}; + +module_i2c_driver(tscs454_i2c_driver); + +MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com"); +MODULE_DESCRIPTION("ASoC TSCS454 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/tscs454.h b/sound/soc/codecs/tscs454.h new file mode 100644 index 000000000000..1142d73d3168 --- /dev/null +++ b/sound/soc/codecs/tscs454.h @@ -0,0 +1,2323 @@ +// SPDX-License-Identifier: GPL-2.0 +// tscs454.h -- TSCS454 ALSA SoC Audio driver +// Copyright 2018 Tempo Semiconductor, Inc. +// Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com> + +#ifndef __REDWOODPUBLIC_H__ +#define __REDWOODPUBLIC_H__ + +#define VIRT_BASE 0x00 +#define PAGE_LEN 0x100 +#define VIRT_PAGE_BASE(page) (VIRT_BASE + (PAGE_LEN * page)) +#define VIRT_ADDR(page, address) (VIRT_PAGE_BASE(page) + address) +#define ADDR(page, virt_address) (virt_address - VIRT_PAGE_BASE(page)) + +#define R_PAGESEL 0x0 +#define R_RESET VIRT_ADDR(0x0, 0x1) +#define R_IRQEN VIRT_ADDR(0x0, 0x2) +#define R_IRQMASK VIRT_ADDR(0x0, 0x3) +#define R_IRQSTAT VIRT_ADDR(0x0, 0x4) +#define R_DEVADD0 VIRT_ADDR(0x0, 0x6) +#define R_DEVID VIRT_ADDR(0x0, 0x8) +#define R_DEVREV VIRT_ADDR(0x0, 0x9) +#define R_PLLSTAT VIRT_ADDR(0x0, 0x0A) +#define R_PLL1CTL VIRT_ADDR(0x0, 0x0B) +#define R_PLL1RDIV VIRT_ADDR(0x0, 0x0C) +#define R_PLL1ODIV VIRT_ADDR(0x0, 0x0D) +#define R_PLL1FDIVL VIRT_ADDR(0x0, 0x0E) +#define R_PLL1FDIVH VIRT_ADDR(0x0, 0x0F) +#define R_PLL2CTL VIRT_ADDR(0x0, 0x10) +#define R_PLL2RDIV VIRT_ADDR(0x0, 0x11) +#define R_PLL2ODIV VIRT_ADDR(0x0, 0x12) +#define R_PLL2FDIVL VIRT_ADDR(0x0, 0x13) +#define R_PLL2FDIVH VIRT_ADDR(0x0, 0x14) +#define R_PLLCTL VIRT_ADDR(0x0, 0x15) +#define R_ISRC VIRT_ADDR(0x0, 0x16) +#define R_SCLKCTL VIRT_ADDR(0x0, 0x18) +#define R_TIMEBASE VIRT_ADDR(0x0, 0x19) +#define R_I2SP1CTL VIRT_ADDR(0x0, 0x1A) +#define R_I2SP2CTL VIRT_ADDR(0x0, 0x1B) +#define R_I2SP3CTL VIRT_ADDR(0x0, 0x1C) +#define R_I2S1MRATE VIRT_ADDR(0x0, 0x1D) +#define R_I2S2MRATE VIRT_ADDR(0x0, 0x1E) +#define R_I2S3MRATE VIRT_ADDR(0x0, 0x1F) +#define R_I2SCMC VIRT_ADDR(0x0, 0x20) +#define R_MCLK2PINC VIRT_ADDR(0x0, 0x21) +#define R_I2SPINC0 VIRT_ADDR(0x0, 0x22) +#define R_I2SPINC1 VIRT_ADDR(0x0, 0x23) +#define R_I2SPINC2 VIRT_ADDR(0x0, 0x24) +#define R_GPIOCTL0 VIRT_ADDR(0x0, 0x25) +#define R_GPIOCTL1 VIRT_ADDR(0x0, 0x26) +#define R_ASRC VIRT_ADDR(0x0, 0x28) +#define R_TDMCTL0 VIRT_ADDR(0x0, 0x2D) +#define R_TDMCTL1 VIRT_ADDR(0x0, 0x2E) +#define R_PCMP2CTL0 VIRT_ADDR(0x0, 0x2F) +#define R_PCMP2CTL1 VIRT_ADDR(0x0, 0x30) +#define R_PCMP3CTL0 VIRT_ADDR(0x0, 0x31) +#define R_PCMP3CTL1 VIRT_ADDR(0x0, 0x32) +#define R_PWRM0 VIRT_ADDR(0x0, 0x33) +#define R_PWRM1 VIRT_ADDR(0x0, 0x34) +#define R_PWRM2 VIRT_ADDR(0x0, 0x35) +#define R_PWRM3 VIRT_ADDR(0x0, 0x36) +#define R_PWRM4 VIRT_ADDR(0x0, 0x37) +#define R_I2SIDCTL VIRT_ADDR(0x0, 0x38) +#define R_I2SODCTL VIRT_ADDR(0x0, 0x39) +#define R_AUDIOMUX1 VIRT_ADDR(0x0, 0x3A) +#define R_AUDIOMUX2 VIRT_ADDR(0x0, 0x3B) +#define R_AUDIOMUX3 VIRT_ADDR(0x0, 0x3C) +#define R_HSDCTL1 VIRT_ADDR(0x1, 0x1) +#define R_HSDCTL2 VIRT_ADDR(0x1, 0x2) +#define R_HSDSTAT VIRT_ADDR(0x1, 0x3) +#define R_HSDDELAY VIRT_ADDR(0x1, 0x4) +#define R_BUTCTL VIRT_ADDR(0x1, 0x5) +#define R_CH0AIC VIRT_ADDR(0x1, 0x6) +#define R_CH1AIC VIRT_ADDR(0x1, 0x7) +#define R_CH2AIC VIRT_ADDR(0x1, 0x8) +#define R_CH3AIC VIRT_ADDR(0x1, 0x9) +#define R_ICTL0 VIRT_ADDR(0x1, 0x0A) +#define R_ICTL1 VIRT_ADDR(0x1, 0x0B) +#define R_MICBIAS VIRT_ADDR(0x1, 0x0C) +#define R_PGACTL0 VIRT_ADDR(0x1, 0x0D) +#define R_PGACTL1 VIRT_ADDR(0x1, 0x0E) +#define R_PGACTL2 VIRT_ADDR(0x1, 0x0F) +#define R_PGACTL3 VIRT_ADDR(0x1, 0x10) +#define R_PGAZ VIRT_ADDR(0x1, 0x11) +#define R_ICH0VOL VIRT_ADDR(0x1, 0x12) +#define R_ICH1VOL VIRT_ADDR(0x1, 0x13) +#define R_ICH2VOL VIRT_ADDR(0x1, 0x14) +#define R_ICH3VOL VIRT_ADDR(0x1, 0x15) +#define R_ASRCILVOL VIRT_ADDR(0x1, 0x16) +#define R_ASRCIRVOL VIRT_ADDR(0x1, 0x17) +#define R_ASRCOLVOL VIRT_ADDR(0x1, 0x18) +#define R_ASRCORVOL VIRT_ADDR(0x1, 0x19) +#define R_IVOLCTLU VIRT_ADDR(0x1, 0x1C) +#define R_ALCCTL0 VIRT_ADDR(0x1, 0x1D) +#define R_ALCCTL1 VIRT_ADDR(0x1, 0x1E) +#define R_ALCCTL2 VIRT_ADDR(0x1, 0x1F) +#define R_ALCCTL3 VIRT_ADDR(0x1, 0x20) +#define R_NGATE VIRT_ADDR(0x1, 0x21) +#define R_DMICCTL VIRT_ADDR(0x1, 0x22) +#define R_DACCTL VIRT_ADDR(0x2, 0x1) +#define R_SPKCTL VIRT_ADDR(0x2, 0x2) +#define R_SUBCTL VIRT_ADDR(0x2, 0x3) +#define R_DCCTL VIRT_ADDR(0x2, 0x4) +#define R_OVOLCTLU VIRT_ADDR(0x2, 0x6) +#define R_MUTEC VIRT_ADDR(0x2, 0x7) +#define R_MVOLL VIRT_ADDR(0x2, 0x8) +#define R_MVOLR VIRT_ADDR(0x2, 0x9) +#define R_HPVOLL VIRT_ADDR(0x2, 0x0A) +#define R_HPVOLR VIRT_ADDR(0x2, 0x0B) +#define R_SPKVOLL VIRT_ADDR(0x2, 0x0C) +#define R_SPKVOLR VIRT_ADDR(0x2, 0x0D) +#define R_SUBVOL VIRT_ADDR(0x2, 0x10) +#define R_COP0 VIRT_ADDR(0x2, 0x11) +#define R_COP1 VIRT_ADDR(0x2, 0x12) +#define R_COPSTAT VIRT_ADDR(0x2, 0x13) +#define R_PWM0 VIRT_ADDR(0x2, 0x14) +#define R_PWM1 VIRT_ADDR(0x2, 0x15) +#define R_PWM2 VIRT_ADDR(0x2, 0x16) +#define R_PWM3 VIRT_ADDR(0x2, 0x17) +#define R_HPSW VIRT_ADDR(0x2, 0x18) +#define R_THERMTS VIRT_ADDR(0x2, 0x19) +#define R_THERMSPK1 VIRT_ADDR(0x2, 0x1A) +#define R_THERMSTAT VIRT_ADDR(0x2, 0x1B) +#define R_SCSTAT VIRT_ADDR(0x2, 0x1C) +#define R_SDMON VIRT_ADDR(0x2, 0x1D) +#define R_SPKEQFILT VIRT_ADDR(0x3, 0x1) +#define R_SPKCRWDL VIRT_ADDR(0x3, 0x2) +#define R_SPKCRWDM VIRT_ADDR(0x3, 0x3) +#define R_SPKCRWDH VIRT_ADDR(0x3, 0x4) +#define R_SPKCRRDL VIRT_ADDR(0x3, 0x5) +#define R_SPKCRRDM VIRT_ADDR(0x3, 0x6) +#define R_SPKCRRDH VIRT_ADDR(0x3, 0x7) +#define R_SPKCRADD VIRT_ADDR(0x3, 0x8) +#define R_SPKCRS VIRT_ADDR(0x3, 0x9) +#define R_SPKMBCEN VIRT_ADDR(0x3, 0x0A) +#define R_SPKMBCCTL VIRT_ADDR(0x3, 0x0B) +#define R_SPKMBCMUG1 VIRT_ADDR(0x3, 0x0C) +#define R_SPKMBCTHR1 VIRT_ADDR(0x3, 0x0D) +#define R_SPKMBCRAT1 VIRT_ADDR(0x3, 0x0E) +#define R_SPKMBCATK1L VIRT_ADDR(0x3, 0x0F) +#define R_SPKMBCATK1H VIRT_ADDR(0x3, 0x10) +#define R_SPKMBCREL1L VIRT_ADDR(0x3, 0x11) +#define R_SPKMBCREL1H VIRT_ADDR(0x3, 0x12) +#define R_SPKMBCMUG2 VIRT_ADDR(0x3, 0x13) +#define R_SPKMBCTHR2 VIRT_ADDR(0x3, 0x14) +#define R_SPKMBCRAT2 VIRT_ADDR(0x3, 0x15) +#define R_SPKMBCATK2L VIRT_ADDR(0x3, 0x16) +#define R_SPKMBCATK2H VIRT_ADDR(0x3, 0x17) +#define R_SPKMBCREL2L VIRT_ADDR(0x3, 0x18) +#define R_SPKMBCREL2H VIRT_ADDR(0x3, 0x19) +#define R_SPKMBCMUG3 VIRT_ADDR(0x3, 0x1A) +#define R_SPKMBCTHR3 VIRT_ADDR(0x3, 0x1B) +#define R_SPKMBCRAT3 VIRT_ADDR(0x3, 0x1C) +#define R_SPKMBCATK3L VIRT_ADDR(0x3, 0x1D) +#define R_SPKMBCATK3H VIRT_ADDR(0x3, 0x1E) +#define R_SPKMBCREL3L VIRT_ADDR(0x3, 0x1F) +#define R_SPKMBCREL3H VIRT_ADDR(0x3, 0x20) +#define R_SPKCLECTL VIRT_ADDR(0x3, 0x21) +#define R_SPKCLEMUG VIRT_ADDR(0x3, 0x22) +#define R_SPKCOMPTHR VIRT_ADDR(0x3, 0x23) +#define R_SPKCOMPRAT VIRT_ADDR(0x3, 0x24) +#define R_SPKCOMPATKL VIRT_ADDR(0x3, 0x25) +#define R_SPKCOMPATKH VIRT_ADDR(0x3, 0x26) +#define R_SPKCOMPRELL VIRT_ADDR(0x3, 0x27) +#define R_SPKCOMPRELH VIRT_ADDR(0x3, 0x28) +#define R_SPKLIMTHR VIRT_ADDR(0x3, 0x29) +#define R_SPKLIMTGT VIRT_ADDR(0x3, 0x2A) +#define R_SPKLIMATKL VIRT_ADDR(0x3, 0x2B) +#define R_SPKLIMATKH VIRT_ADDR(0x3, 0x2C) +#define R_SPKLIMRELL VIRT_ADDR(0x3, 0x2D) +#define R_SPKLIMRELH VIRT_ADDR(0x3, 0x2E) +#define R_SPKEXPTHR VIRT_ADDR(0x3, 0x2F) +#define R_SPKEXPRAT VIRT_ADDR(0x3, 0x30) +#define R_SPKEXPATKL VIRT_ADDR(0x3, 0x31) +#define R_SPKEXPATKH VIRT_ADDR(0x3, 0x32) +#define R_SPKEXPRELL VIRT_ADDR(0x3, 0x33) +#define R_SPKEXPRELH VIRT_ADDR(0x3, 0x34) +#define R_SPKFXCTL VIRT_ADDR(0x3, 0x35) +#define R_DACEQFILT VIRT_ADDR(0x4, 0x1) +#define R_DACCRWDL VIRT_ADDR(0x4, 0x2) +#define R_DACCRWDM VIRT_ADDR(0x4, 0x3) +#define R_DACCRWDH VIRT_ADDR(0x4, 0x4) +#define R_DACCRRDL VIRT_ADDR(0x4, 0x5) +#define R_DACCRRDM VIRT_ADDR(0x4, 0x6) +#define R_DACCRRDH VIRT_ADDR(0x4, 0x7) +#define R_DACCRADD VIRT_ADDR(0x4, 0x8) +#define R_DACCRS VIRT_ADDR(0x4, 0x9) +#define R_DACMBCEN VIRT_ADDR(0x4, 0x0A) +#define R_DACMBCCTL VIRT_ADDR(0x4, 0x0B) +#define R_DACMBCMUG1 VIRT_ADDR(0x4, 0x0C) +#define R_DACMBCTHR1 VIRT_ADDR(0x4, 0x0D) +#define R_DACMBCRAT1 VIRT_ADDR(0x4, 0x0E) +#define R_DACMBCATK1L VIRT_ADDR(0x4, 0x0F) +#define R_DACMBCATK1H VIRT_ADDR(0x4, 0x10) +#define R_DACMBCREL1L VIRT_ADDR(0x4, 0x11) +#define R_DACMBCREL1H VIRT_ADDR(0x4, 0x12) +#define R_DACMBCMUG2 VIRT_ADDR(0x4, 0x13) +#define R_DACMBCTHR2 VIRT_ADDR(0x4, 0x14) +#define R_DACMBCRAT2 VIRT_ADDR(0x4, 0x15) +#define R_DACMBCATK2L VIRT_ADDR(0x4, 0x16) +#define R_DACMBCATK2H VIRT_ADDR(0x4, 0x17) +#define R_DACMBCREL2L VIRT_ADDR(0x4, 0x18) +#define R_DACMBCREL2H VIRT_ADDR(0x4, 0x19) +#define R_DACMBCMUG3 VIRT_ADDR(0x4, 0x1A) +#define R_DACMBCTHR3 VIRT_ADDR(0x4, 0x1B) +#define R_DACMBCRAT3 VIRT_ADDR(0x4, 0x1C) +#define R_DACMBCATK3L VIRT_ADDR(0x4, 0x1D) +#define R_DACMBCATK3H VIRT_ADDR(0x4, 0x1E) +#define R_DACMBCREL3L VIRT_ADDR(0x4, 0x1F) +#define R_DACMBCREL3H VIRT_ADDR(0x4, 0x20) +#define R_DACCLECTL VIRT_ADDR(0x4, 0x21) +#define R_DACCLEMUG VIRT_ADDR(0x4, 0x22) +#define R_DACCOMPTHR VIRT_ADDR(0x4, 0x23) +#define R_DACCOMPRAT VIRT_ADDR(0x4, 0x24) +#define R_DACCOMPATKL VIRT_ADDR(0x4, 0x25) +#define R_DACCOMPATKH VIRT_ADDR(0x4, 0x26) +#define R_DACCOMPRELL VIRT_ADDR(0x4, 0x27) +#define R_DACCOMPRELH VIRT_ADDR(0x4, 0x28) +#define R_DACLIMTHR VIRT_ADDR(0x4, 0x29) +#define R_DACLIMTGT VIRT_ADDR(0x4, 0x2A) +#define R_DACLIMATKL VIRT_ADDR(0x4, 0x2B) +#define R_DACLIMATKH VIRT_ADDR(0x4, 0x2C) +#define R_DACLIMRELL VIRT_ADDR(0x4, 0x2D) +#define R_DACLIMRELH VIRT_ADDR(0x4, 0x2E) +#define R_DACEXPTHR VIRT_ADDR(0x4, 0x2F) +#define R_DACEXPRAT VIRT_ADDR(0x4, 0x30) +#define R_DACEXPATKL VIRT_ADDR(0x4, 0x31) +#define R_DACEXPATKH VIRT_ADDR(0x4, 0x32) +#define R_DACEXPRELL VIRT_ADDR(0x4, 0x33) +#define R_DACEXPRELH VIRT_ADDR(0x4, 0x34) +#define R_DACFXCTL VIRT_ADDR(0x4, 0x35) +#define R_SUBEQFILT VIRT_ADDR(0x5, 0x1) +#define R_SUBCRWDL VIRT_ADDR(0x5, 0x2) +#define R_SUBCRWDM VIRT_ADDR(0x5, 0x3) +#define R_SUBCRWDH VIRT_ADDR(0x5, 0x4) +#define R_SUBCRRDL VIRT_ADDR(0x5, 0x5) +#define R_SUBCRRDM VIRT_ADDR(0x5, 0x6) +#define R_SUBCRRDH VIRT_ADDR(0x5, 0x7) +#define R_SUBCRADD VIRT_ADDR(0x5, 0x8) +#define R_SUBCRS VIRT_ADDR(0x5, 0x9) +#define R_SUBMBCEN VIRT_ADDR(0x5, 0x0A) +#define R_SUBMBCCTL VIRT_ADDR(0x5, 0x0B) +#define R_SUBMBCMUG1 VIRT_ADDR(0x5, 0x0C) +#define R_SUBMBCTHR1 VIRT_ADDR(0x5, 0x0D) +#define R_SUBMBCRAT1 VIRT_ADDR(0x5, 0x0E) +#define R_SUBMBCATK1L VIRT_ADDR(0x5, 0x0F) +#define R_SUBMBCATK1H VIRT_ADDR(0x5, 0x10) +#define R_SUBMBCREL1L VIRT_ADDR(0x5, 0x11) +#define R_SUBMBCREL1H VIRT_ADDR(0x5, 0x12) +#define R_SUBMBCMUG2 VIRT_ADDR(0x5, 0x13) +#define R_SUBMBCTHR2 VIRT_ADDR(0x5, 0x14) +#define R_SUBMBCRAT2 VIRT_ADDR(0x5, 0x15) +#define R_SUBMBCATK2L VIRT_ADDR(0x5, 0x16) +#define R_SUBMBCATK2H VIRT_ADDR(0x5, 0x17) +#define R_SUBMBCREL2L VIRT_ADDR(0x5, 0x18) +#define R_SUBMBCREL2H VIRT_ADDR(0x5, 0x19) +#define R_SUBMBCMUG3 VIRT_ADDR(0x5, 0x1A) +#define R_SUBMBCTHR3 VIRT_ADDR(0x5, 0x1B) +#define R_SUBMBCRAT3 VIRT_ADDR(0x5, 0x1C) +#define R_SUBMBCATK3L VIRT_ADDR(0x5, 0x1D) +#define R_SUBMBCATK3H VIRT_ADDR(0x5, 0x1E) +#define R_SUBMBCREL3L VIRT_ADDR(0x5, 0x1F) +#define R_SUBMBCREL3H VIRT_ADDR(0x5, 0x20) +#define R_SUBCLECTL VIRT_ADDR(0x5, 0x21) +#define R_SUBCLEMUG VIRT_ADDR(0x5, 0x22) +#define R_SUBCOMPTHR VIRT_ADDR(0x5, 0x23) +#define R_SUBCOMPRAT VIRT_ADDR(0x5, 0x24) +#define R_SUBCOMPATKL VIRT_ADDR(0x5, 0x25) +#define R_SUBCOMPATKH VIRT_ADDR(0x5, 0x26) +#define R_SUBCOMPRELL VIRT_ADDR(0x5, 0x27) +#define R_SUBCOMPRELH VIRT_ADDR(0x5, 0x28) +#define R_SUBLIMTHR VIRT_ADDR(0x5, 0x29) +#define R_SUBLIMTGT VIRT_ADDR(0x5, 0x2A) +#define R_SUBLIMATKL VIRT_ADDR(0x5, 0x2B) +#define R_SUBLIMATKH VIRT_ADDR(0x5, 0x2C) +#define R_SUBLIMRELL VIRT_ADDR(0x5, 0x2D) +#define R_SUBLIMRELH VIRT_ADDR(0x5, 0x2E) +#define R_SUBEXPTHR VIRT_ADDR(0x5, 0x2F) +#define R_SUBEXPRAT VIRT_ADDR(0x5, 0x30) +#define R_SUBEXPATKL VIRT_ADDR(0x5, 0x31) +#define R_SUBEXPATKH VIRT_ADDR(0x5, 0x32) +#define R_SUBEXPRELL VIRT_ADDR(0x5, 0x33) +#define R_SUBEXPRELH VIRT_ADDR(0x5, 0x34) +#define R_SUBFXCTL VIRT_ADDR(0x5, 0x35) + +// *** PLLCTL *** +#define FB_PLLCTL_VCCI_PLL 6 +#define FM_PLLCTL_VCCI_PLL 0xC0 + +#define FB_PLLCTL_RZ_PLL 3 +#define FM_PLLCTL_RZ_PLL 0x38 + +#define FB_PLLCTL_CP_PLL 0 +#define FM_PLLCTL_CP_PLL 0x7 + +// *** PLLRDIV *** +#define FB_PLLRDIV_REFDIV_PLL 0 +#define FM_PLLRDIV_REFDIV_PLL 0xFF + +// *** PLLODIV *** +#define FB_PLLODIV_OUTDIV_PLL 0 +#define FM_PLLODIV_OUTDIV_PLL 0xFF + +// *** PLLFDIVL *** +#define FB_PLLFDIVL_FBDIVL_PLL 0 +#define FM_PLLFDIVL_FBDIVL_PLL 0xFF + +// *** PLLFDIVH *** +#define FB_PLLFDIVH_FBDIVH_PLL 0 +#define FM_PLLFDIVH_FBDIVH_PLL 0xF + +// *** I2SPCTL *** +#define FB_I2SPCTL_BCLKSTAT 7 +#define FM_I2SPCTL_BCLKSTAT 0x80 +#define FV_BCLKSTAT_LOST 0x80 +#define FV_BCLKSTAT_NOT_LOST 0x0 + +#define FB_I2SPCTL_BCLKP 6 +#define FM_I2SPCTL_BCLKP 0x40 +#define FV_BCLKP_NOT_INVERTED 0x0 +#define FV_BCLKP_INVERTED 0x40 + +#define FB_I2SPCTL_PORTMS 5 +#define FM_I2SPCTL_PORTMS 0x20 +#define FV_PORTMS_SLAVE 0x0 +#define FV_PORTMS_MASTER 0x20 + +#define FB_I2SPCTL_LRCLKP 4 +#define FM_I2SPCTL_LRCLKP 0x10 +#define FV_LRCLKP_NOT_INVERTED 0x0 +#define FV_LRCLKP_INVERTED 0x10 + +#define FB_I2SPCTL_WL 2 +#define FM_I2SPCTL_WL 0xC +#define FV_WL_16 0x0 +#define FV_WL_20 0x4 +#define FV_WL_24 0x8 +#define FV_WL_32 0xC + +#define FB_I2SPCTL_FORMAT 0 +#define FM_I2SPCTL_FORMAT 0x3 +#define FV_FORMAT_RIGHT 0x0 +#define FV_FORMAT_LEFT 0x1 +#define FV_FORMAT_I2S 0x2 +#define FV_FORMAT_TDM 0x3 + +// *** I2SMRATE *** +#define FB_I2SMRATE_I2SMCLKHALF 7 +#define FM_I2SMRATE_I2SMCLKHALF 0x80 +#define FV_I2SMCLKHALF_I2S1MCLKDIV_DIV_2 0x0 +#define FV_I2SMCLKHALF_I2S1MCLKDIV_ONLY 0x80 + +#define FB_I2SMRATE_I2SMCLKDIV 5 +#define FM_I2SMRATE_I2SMCLKDIV 0x60 +#define FV_I2SMCLKDIV_125 0x0 +#define FV_I2SMCLKDIV_128 0x20 +#define FV_I2SMCLKDIV_136 0x40 +#define FV_I2SMCLKDIV_192 0x60 + +#define FB_I2SMRATE_I2SMBR 3 +#define FM_I2SMRATE_I2SMBR 0x18 +#define FV_I2SMBR_32 0x0 +#define FV_I2SMBR_44PT1 0x8 +#define FV_I2SMBR_48 0x10 +#define FV_I2SMBR_MCLK_MODE 0x18 + +#define FB_I2SMRATE_I2SMBM 0 +#define FM_I2SMRATE_I2SMBM 0x3 +#define FV_I2SMBM_0PT25 0x0 +#define FV_I2SMBM_0PT5 0x1 +#define FV_I2SMBM_1 0x2 +#define FV_I2SMBM_2 0x3 + +// *** PCMPCTL0 *** +#define FB_PCMPCTL0_PCMFLENP 2 +#define FM_PCMPCTL0_PCMFLENP 0x4 +#define FV_PCMFLENP_128 0x0 +#define FV_PCMFLENP_256 0x4 + +#define FB_PCMPCTL0_SLSYNCP 1 +#define FM_PCMPCTL0_SLSYNCP 0x2 +#define FV_SLSYNCP_SHORT 0x0 +#define FV_SLSYNCP_LONG 0x2 + +#define FB_PCMPCTL0_BDELAYP 0 +#define FM_PCMPCTL0_BDELAYP 0x1 +#define FV_BDELAYP_NO_DELAY 0x0 +#define FV_BDELAYP_1BCLK_DELAY 0x1 + +// *** PCMPCTL1 *** +#define FB_PCMPCTL1_PCMMOMP 6 +#define FM_PCMPCTL1_PCMMOMP 0x40 + +#define FB_PCMPCTL1_PCMSOP 5 +#define FM_PCMPCTL1_PCMSOP 0x20 +#define FV_PCMSOP_1 0x0 +#define FV_PCMSOP_2 0x20 + +#define FB_PCMPCTL1_PCMDSSP 3 +#define FM_PCMPCTL1_PCMDSSP 0x18 +#define FV_PCMDSSP_16 0x0 +#define FV_PCMDSSP_24 0x8 +#define FV_PCMDSSP_32 0x10 + +#define FB_PCMPCTL1_PCMMIMP 1 +#define FM_PCMPCTL1_PCMMIMP 0x2 + +#define FB_PCMPCTL1_PCMSIP 0 +#define FM_PCMPCTL1_PCMSIP 0x1 +#define FV_PCMSIP_1 0x0 +#define FV_PCMSIP_2 0x1 + +// *** CHAIC *** +#define FB_CHAIC_MICBST 4 +#define FM_CHAIC_MICBST 0x30 + +// *** PGACTL *** +#define FB_PGACTL_PGAMUTE 7 +#define FM_PGACTL_PGAMUTE 0x80 + +#define FB_PGACTL_PGAVOL 0 +#define FM_PGACTL_PGAVOL 0x3F + +// *** ICHVOL *** +#define FB_ICHVOL_ICHVOL 0 +#define FM_ICHVOL_ICHVOL 0xFF + +// *** SPKMBCMUG *** +#define FB_SPKMBCMUG_PHASE 5 +#define FM_SPKMBCMUG_PHASE 0x20 + +#define FB_SPKMBCMUG_MUGAIN 0 +#define FM_SPKMBCMUG_MUGAIN 0x1F + +// *** SPKMBCTHR *** +#define FB_SPKMBCTHR_THRESH 0 +#define FM_SPKMBCTHR_THRESH 0xFF + +// *** SPKMBCRAT *** +#define FB_SPKMBCRAT_RATIO 0 +#define FM_SPKMBCRAT_RATIO 0x1F + +// *** SPKMBCATKL *** +#define FB_SPKMBCATKL_TCATKL 0 +#define FM_SPKMBCATKL_TCATKL 0xFF + +// *** SPKMBCATKH *** +#define FB_SPKMBCATKH_TCATKH 0 +#define FM_SPKMBCATKH_TCATKH 0xFF + +// *** SPKMBCRELL *** +#define FB_SPKMBCRELL_TCRELL 0 +#define FM_SPKMBCRELL_TCRELL 0xFF + +// *** SPKMBCRELH *** +#define FB_SPKMBCRELH_TCRELH 0 +#define FM_SPKMBCRELH_TCRELH 0xFF + +// *** DACMBCMUG *** +#define FB_DACMBCMUG_PHASE 5 +#define FM_DACMBCMUG_PHASE 0x20 + +#define FB_DACMBCMUG_MUGAIN 0 +#define FM_DACMBCMUG_MUGAIN 0x1F + +// *** DACMBCTHR *** +#define FB_DACMBCTHR_THRESH 0 +#define FM_DACMBCTHR_THRESH 0xFF + +// *** DACMBCRAT *** +#define FB_DACMBCRAT_RATIO 0 +#define FM_DACMBCRAT_RATIO 0x1F + +// *** DACMBCATKL *** +#define FB_DACMBCATKL_TCATKL 0 +#define FM_DACMBCATKL_TCATKL 0xFF + +// *** DACMBCATKH *** +#define FB_DACMBCATKH_TCATKH 0 +#define FM_DACMBCATKH_TCATKH 0xFF + +// *** DACMBCRELL *** +#define FB_DACMBCRELL_TCRELL 0 +#define FM_DACMBCRELL_TCRELL 0xFF + +// *** DACMBCRELH *** +#define FB_DACMBCRELH_TCRELH 0 +#define FM_DACMBCRELH_TCRELH 0xFF + +// *** SUBMBCMUG *** +#define FB_SUBMBCMUG_PHASE 5 +#define FM_SUBMBCMUG_PHASE 0x20 + +#define FB_SUBMBCMUG_MUGAIN 0 +#define FM_SUBMBCMUG_MUGAIN 0x1F + +// *** SUBMBCTHR *** +#define FB_SUBMBCTHR_THRESH 0 +#define FM_SUBMBCTHR_THRESH 0xFF + +// *** SUBMBCRAT *** +#define FB_SUBMBCRAT_RATIO 0 +#define FM_SUBMBCRAT_RATIO 0x1F + +// *** SUBMBCATKL *** +#define FB_SUBMBCATKL_TCATKL 0 +#define FM_SUBMBCATKL_TCATKL 0xFF + +// *** SUBMBCATKH *** +#define FB_SUBMBCATKH_TCATKH 0 +#define FM_SUBMBCATKH_TCATKH 0xFF + +// *** SUBMBCRELL *** +#define FB_SUBMBCRELL_TCRELL 0 +#define FM_SUBMBCRELL_TCRELL 0xFF + +// *** SUBMBCRELH *** +#define FB_SUBMBCRELH_TCRELH 0 +#define FM_SUBMBCRELH_TCRELH 0xFF + +// *** PAGESEL *** +#define FB_PAGESEL_PAGESEL 0 +#define FM_PAGESEL_PAGESEL 0xFF + +// *** RESET *** +#define FB_RESET_RESET 0 +#define FM_RESET_RESET 0xFF +#define FV_RESET_PWR_ON_DEFAULTS 0x85 + +// *** IRQEN *** +#define FB_IRQEN_THRMINTEN 6 +#define FM_IRQEN_THRMINTEN 0x40 +#define FV_THRMINTEN_ENABLED 0x40 +#define FV_THRMINTEN_DISABLED 0x0 + +#define FB_IRQEN_HBPINTEN 5 +#define FM_IRQEN_HBPINTEN 0x20 +#define FV_HBPINTEN_ENABLED 0x20 +#define FV_HBPINTEN_DISABLED 0x0 + +#define FB_IRQEN_HSDINTEN 4 +#define FM_IRQEN_HSDINTEN 0x10 +#define FV_HSDINTEN_ENABLED 0x10 +#define FV_HSDINTEN_DISABLED 0x0 + +#define FB_IRQEN_HPDINTEN 3 +#define FM_IRQEN_HPDINTEN 0x8 +#define FV_HPDINTEN_ENABLED 0x8 +#define FV_HPDINTEN_DISABLED 0x0 + +#define FB_IRQEN_GPIO3INTEN 1 +#define FM_IRQEN_GPIO3INTEN 0x2 +#define FV_GPIO3INTEN_ENABLED 0x2 +#define FV_GPIO3INTEN_DISABLED 0x0 + +#define FB_IRQEN_GPIO2INTEN 0 +#define FM_IRQEN_GPIO2INTEN 0x1 +#define FV_GPIO2INTEN_ENABLED 0x1 +#define FV_GPIO2INTEN_DISABLED 0x0 + +#define IRQEN_GPIOINTEN_ENABLED 0x1 +#define IRQEN_GPIOINTEN_DISABLED 0x0 + +// *** IRQMASK *** +#define FB_IRQMASK_THRMIM 6 +#define FM_IRQMASK_THRMIM 0x40 +#define FV_THRMIM_MASKED 0x0 +#define FV_THRMIM_NOT_MASKED 0x40 + +#define FB_IRQMASK_HBPIM 5 +#define FM_IRQMASK_HBPIM 0x20 +#define FV_HBPIM_MASKED 0x0 +#define FV_HBPIM_NOT_MASKED 0x20 + +#define FB_IRQMASK_HSDIM 4 +#define FM_IRQMASK_HSDIM 0x10 +#define FV_HSDIM_MASKED 0x0 +#define FV_HSDIM_NOT_MASKED 0x10 + +#define FB_IRQMASK_HPDIM 3 +#define FM_IRQMASK_HPDIM 0x8 +#define FV_HPDIM_MASKED 0x0 +#define FV_HPDIM_NOT_MASKED 0x8 + +#define FB_IRQMASK_GPIO3M 1 +#define FM_IRQMASK_GPIO3M 0x2 +#define FV_GPIO3M_MASKED 0x0 +#define FV_GPIO3M_NOT_MASKED 0x2 + +#define FB_IRQMASK_GPIO2M 0 +#define FM_IRQMASK_GPIO2M 0x1 +#define FV_GPIO2M_MASKED 0x0 +#define FV_GPIO2M_NOT_MASKED 0x1 + +#define IRQMASK_GPIOM_MASKED 0x0 +#define IRQMASK_GPIOM_NOT_MASKED 0x1 + +// *** IRQSTAT *** +#define FB_IRQSTAT_THRMINT 6 +#define FM_IRQSTAT_THRMINT 0x40 +#define FV_THRMINT_INTERRUPTED 0x40 +#define FV_THRMINT_NOT_INTERRUPTED 0x0 + +#define FB_IRQSTAT_HBPINT 5 +#define FM_IRQSTAT_HBPINT 0x20 +#define FV_HBPINT_INTERRUPTED 0x20 +#define FV_HBPINT_NOT_INTERRUPTED 0x0 + +#define FB_IRQSTAT_HSDINT 4 +#define FM_IRQSTAT_HSDINT 0x10 +#define FV_HSDINT_INTERRUPTED 0x10 +#define FV_HSDINT_NOT_INTERRUPTED 0x0 + +#define FB_IRQSTAT_HPDINT 3 +#define FM_IRQSTAT_HPDINT 0x8 +#define FV_HPDINT_INTERRUPTED 0x8 +#define FV_HPDINT_NOT_INTERRUPTED 0x0 + +#define FB_IRQSTAT_GPIO3INT 1 +#define FM_IRQSTAT_GPIO3INT 0x2 +#define FV_GPIO3INT_INTERRUPTED 0x2 +#define FV_GPIO3INT_NOT_INTERRUPTED 0x0 + +#define FB_IRQSTAT_GPIO2INT 0 +#define FM_IRQSTAT_GPIO2INT 0x1 +#define FV_GPIO2INT_INTERRUPTED 0x1 +#define FV_GPIO2INT_NOT_INTERRUPTED 0x0 + +#define IRQSTAT_GPIOINT_INTERRUPTED 0x1 +#define IRQSTAT_GPIOINT_NOT_INTERRUPTED 0x0 + +// *** DEVADD0 *** +#define FB_DEVADD0_DEVADD0 1 +#define FM_DEVADD0_DEVADD0 0xFE + +#define FB_DEVADD0_I2C_ADDRLK 0 +#define FM_DEVADD0_I2C_ADDRLK 0x1 +#define FV_I2C_ADDRLK_LOCK 0x1 + +// *** DEVID *** +#define FB_DEVID_DEV_ID 0 +#define FM_DEVID_DEV_ID 0xFF + +// *** DEVREV *** +#define FB_DEVREV_MAJ_REV 4 +#define FM_DEVREV_MAJ_REV 0xF0 + +#define FB_DEVREV_MIN_REV 0 +#define FM_DEVREV_MIN_REV 0xF + +// *** PLLSTAT *** +#define FB_PLLSTAT_PLL2LK 1 +#define FM_PLLSTAT_PLL2LK 0x2 +#define FV_PLL2LK_LOCKED 0x2 +#define FV_PLL2LK_UNLOCKED 0x0 + +#define FB_PLLSTAT_PLL1LK 0 +#define FM_PLLSTAT_PLL1LK 0x1 +#define FV_PLL1LK_LOCKED 0x1 +#define FV_PLL1LK_UNLOCKED 0x0 + +#define PLLSTAT_PLLLK_LOCKED 0x1 +#define PLLSTAT_PLLLK_UNLOCKED 0x0 + +// *** PLLCTL *** +#define FB_PLLCTL_PU_PLL2 7 +#define FM_PLLCTL_PU_PLL2 0x80 +#define FV_PU_PLL2_PWR_UP 0x80 +#define FV_PU_PLL2_PWR_DWN 0x0 + +#define FB_PLLCTL_PU_PLL1 6 +#define FM_PLLCTL_PU_PLL1 0x40 +#define FV_PU_PLL1_PWR_UP 0x40 +#define FV_PU_PLL1_PWR_DWN 0x0 + +#define FB_PLLCTL_PLL2CLKEN 5 +#define FM_PLLCTL_PLL2CLKEN 0x20 +#define FV_PLL2CLKEN_ENABLE 0x20 +#define FV_PLL2CLKEN_DISABLE 0x0 + +#define FB_PLLCTL_PLL1CLKEN 4 +#define FM_PLLCTL_PLL1CLKEN 0x10 +#define FV_PLL1CLKEN_ENABLE 0x10 +#define FV_PLL1CLKEN_DISABLE 0x0 + +#define FB_PLLCTL_BCLKSEL 2 +#define FM_PLLCTL_BCLKSEL 0xC +#define FV_BCLKSEL_BCLK1 0x0 +#define FV_BCLKSEL_BCLK2 0x4 +#define FV_BCLKSEL_BCLK3 0x8 + +#define FB_PLLCTL_PLLISEL 0 +#define FM_PLLCTL_PLLISEL 0x3 +#define FV_PLLISEL_XTAL 0x0 +#define FV_PLLISEL_MCLK1 0x1 +#define FV_PLLISEL_MCLK2 0x2 +#define FV_PLLISEL_BCLK 0x3 + +#define PLLCTL_PU_PLL_PWR_UP 0x1 +#define PLLCTL_PU_PLL_PWR_DWN 0x0 +#define PLLCTL_PLLCLKEN_ENABLE 0x1 +#define PLLCTL_PLLCLKEN_DISABLE 0x0 + +// *** ISRC *** +#define FB_ISRC_IBR 2 +#define FM_ISRC_IBR 0x4 +#define FV_IBR_44PT1 0x0 +#define FV_IBR_48 0x4 + +#define FB_ISRC_IBM 0 +#define FM_ISRC_IBM 0x3 +#define FV_IBM_0PT25 0x0 +#define FV_IBM_0PT5 0x1 +#define FV_IBM_1 0x2 +#define FV_IBM_2 0x3 + +// *** SCLKCTL *** +#define FB_SCLKCTL_ASDM 6 +#define FM_SCLKCTL_ASDM 0xC0 +#define FV_ASDM_HALF 0x40 +#define FV_ASDM_FULL 0x80 +#define FV_ASDM_AUTO 0xC0 + +#define FB_SCLKCTL_DSDM 4 +#define FM_SCLKCTL_DSDM 0x30 +#define FV_DSDM_HALF 0x10 +#define FV_DSDM_FULL 0x20 +#define FV_DSDM_AUTO 0x30 + +// *** TIMEBASE *** +#define FB_TIMEBASE_TIMEBASE 0 +#define FM_TIMEBASE_TIMEBASE 0xFF + +// *** I2SCMC *** +#define FB_I2SCMC_BCMP3 4 +#define FM_I2SCMC_BCMP3 0x30 +#define FV_BCMP3_AUTO 0x0 +#define FV_BCMP3_32X 0x10 +#define FV_BCMP3_40X 0x20 +#define FV_BCMP3_64X 0x30 + +#define FB_I2SCMC_BCMP2 2 +#define FM_I2SCMC_BCMP2 0xC +#define FV_BCMP2_AUTO 0x0 +#define FV_BCMP2_32X 0x4 +#define FV_BCMP2_40X 0x8 +#define FV_BCMP2_64X 0xC + +#define FB_I2SCMC_BCMP1 0 +#define FM_I2SCMC_BCMP1 0x3 +#define FV_BCMP1_AUTO 0x0 +#define FV_BCMP1_32X 0x1 +#define FV_BCMP1_40X 0x2 +#define FV_BCMP1_64X 0x3 + +#define I2SCMC_BCMP_AUTO 0x0 +#define I2SCMC_BCMP_32X 0x1 +#define I2SCMC_BCMP_40X 0x2 +#define I2SCMC_BCMP_64X 0x3 + +// *** MCLK2PINC *** +#define FB_MCLK2PINC_SLEWOUT 4 +#define FM_MCLK2PINC_SLEWOUT 0xF0 + +#define FB_MCLK2PINC_MCLK2IO 2 +#define FM_MCLK2PINC_MCLK2IO 0x4 +#define FV_MCLK2IO_INPUT 0x0 +#define FV_MCLK2IO_OUTPUT 0x4 + +#define FB_MCLK2PINC_MCLK2OS 0 +#define FM_MCLK2PINC_MCLK2OS 0x3 +#define FV_MCLK2OS_24PT576 0x0 +#define FV_MCLK2OS_22PT5792 0x1 +#define FV_MCLK2OS_PLL2 0x2 + +// *** I2SPINC0 *** +#define FB_I2SPINC0_SDO3TRI 7 +#define FM_I2SPINC0_SDO3TRI 0x80 + +#define FB_I2SPINC0_SDO2TRI 6 +#define FM_I2SPINC0_SDO2TRI 0x40 + +#define FB_I2SPINC0_SDO1TRI 5 +#define FM_I2SPINC0_SDO1TRI 0x20 + +#define FB_I2SPINC0_PCM3TRI 2 +#define FM_I2SPINC0_PCM3TRI 0x4 + +#define FB_I2SPINC0_PCM2TRI 1 +#define FM_I2SPINC0_PCM2TRI 0x2 + +#define FB_I2SPINC0_PCM1TRI 0 +#define FM_I2SPINC0_PCM1TRI 0x1 + +// *** I2SPINC1 *** +#define FB_I2SPINC1_SDO3PDD 2 +#define FM_I2SPINC1_SDO3PDD 0x4 + +#define FB_I2SPINC1_SDO2PDD 1 +#define FM_I2SPINC1_SDO2PDD 0x2 + +#define FB_I2SPINC1_SDO1PDD 0 +#define FM_I2SPINC1_SDO1PDD 0x1 + +// *** I2SPINC2 *** +#define FB_I2SPINC2_LR3PDD 5 +#define FM_I2SPINC2_LR3PDD 0x20 + +#define FB_I2SPINC2_BC3PDD 4 +#define FM_I2SPINC2_BC3PDD 0x10 + +#define FB_I2SPINC2_LR2PDD 3 +#define FM_I2SPINC2_LR2PDD 0x8 + +#define FB_I2SPINC2_BC2PDD 2 +#define FM_I2SPINC2_BC2PDD 0x4 + +#define FB_I2SPINC2_LR1PDD 1 +#define FM_I2SPINC2_LR1PDD 0x2 + +#define FB_I2SPINC2_BC1PDD 0 +#define FM_I2SPINC2_BC1PDD 0x1 + +// *** GPIOCTL0 *** +#define FB_GPIOCTL0_GPIO3INTP 7 +#define FM_GPIOCTL0_GPIO3INTP 0x80 + +#define FB_GPIOCTL0_GPIO2INTP 6 +#define FM_GPIOCTL0_GPIO2INTP 0x40 + +#define FB_GPIOCTL0_GPIO3CFG 5 +#define FM_GPIOCTL0_GPIO3CFG 0x20 + +#define FB_GPIOCTL0_GPIO2CFG 4 +#define FM_GPIOCTL0_GPIO2CFG 0x10 + +#define FB_GPIOCTL0_GPIO3IO 3 +#define FM_GPIOCTL0_GPIO3IO 0x8 + +#define FB_GPIOCTL0_GPIO2IO 2 +#define FM_GPIOCTL0_GPIO2IO 0x4 + +#define FB_GPIOCTL0_GPIO1IO 1 +#define FM_GPIOCTL0_GPIO1IO 0x2 + +#define FB_GPIOCTL0_GPIO0IO 0 +#define FM_GPIOCTL0_GPIO0IO 0x1 + +// *** GPIOCTL1 *** +#define FB_GPIOCTL1_GPIO3 7 +#define FM_GPIOCTL1_GPIO3 0x80 + +#define FB_GPIOCTL1_GPIO2 6 +#define FM_GPIOCTL1_GPIO2 0x40 + +#define FB_GPIOCTL1_GPIO1 5 +#define FM_GPIOCTL1_GPIO1 0x20 + +#define FB_GPIOCTL1_GPIO0 4 +#define FM_GPIOCTL1_GPIO0 0x10 + +#define FB_GPIOCTL1_GPIO3RD 3 +#define FM_GPIOCTL1_GPIO3RD 0x8 + +#define FB_GPIOCTL1_GPIO2RD 2 +#define FM_GPIOCTL1_GPIO2RD 0x4 + +#define FB_GPIOCTL1_GPIO1RD 1 +#define FM_GPIOCTL1_GPIO1RD 0x2 + +#define FB_GPIOCTL1_GPIO0RD 0 +#define FM_GPIOCTL1_GPIO0RD 0x1 + +// *** ASRC *** +#define FB_ASRC_ASRCOBW 7 +#define FM_ASRC_ASRCOBW 0x80 + +#define FB_ASRC_ASRCIBW 6 +#define FM_ASRC_ASRCIBW 0x40 + +#define FB_ASRC_ASRCOB 5 +#define FM_ASRC_ASRCOB 0x20 +#define FV_ASRCOB_ACTIVE 0x0 +#define FV_ASRCOB_BYPASSED 0x20 + +#define FB_ASRC_ASRCIB 4 +#define FM_ASRC_ASRCIB 0x10 +#define FV_ASRCIB_ACTIVE 0x0 +#define FV_ASRCIB_BYPASSED 0x10 + +#define FB_ASRC_ASRCOL 3 +#define FM_ASRC_ASRCOL 0x8 + +#define FB_ASRC_ASRCIL 2 +#define FM_ASRC_ASRCIL 0x4 + +// *** TDMCTL0 *** +#define FB_TDMCTL0_TDMMD 2 +#define FM_TDMCTL0_TDMMD 0x4 +#define FV_TDMMD_200 0x0 +#define FV_TDMMD_256 0x4 + +#define FB_TDMCTL0_SLSYNC 1 +#define FM_TDMCTL0_SLSYNC 0x2 +#define FV_SLSYNC_SHORT 0x0 +#define FV_SLSYNC_LONG 0x2 + +#define FB_TDMCTL0_BDELAY 0 +#define FM_TDMCTL0_BDELAY 0x1 +#define FV_BDELAY_NO_DELAY 0x0 +#define FV_BDELAY_1BCLK_DELAY 0x1 + +// *** TDMCTL1 *** +#define FB_TDMCTL1_TDMSO 5 +#define FM_TDMCTL1_TDMSO 0x60 +#define FV_TDMSO_2 0x0 +#define FV_TDMSO_4 0x20 +#define FV_TDMSO_6 0x40 + +#define FB_TDMCTL1_TDMDSS 3 +#define FM_TDMCTL1_TDMDSS 0x18 +#define FV_TDMDSS_16 0x0 +#define FV_TDMDSS_24 0x10 +#define FV_TDMDSS_32 0x18 + +#define FB_TDMCTL1_TDMSI 0 +#define FM_TDMCTL1_TDMSI 0x3 +#define FV_TDMSI_2 0x0 +#define FV_TDMSI_4 0x1 +#define FV_TDMSI_6 0x2 + +// *** PWRM0 *** +#define FB_PWRM0_INPROC3PU 6 +#define FM_PWRM0_INPROC3PU 0x40 + +#define FB_PWRM0_INPROC2PU 5 +#define FM_PWRM0_INPROC2PU 0x20 + +#define FB_PWRM0_INPROC1PU 4 +#define FM_PWRM0_INPROC1PU 0x10 + +#define FB_PWRM0_INPROC0PU 3 +#define FM_PWRM0_INPROC0PU 0x8 + +#define FB_PWRM0_MICB2PU 2 +#define FM_PWRM0_MICB2PU 0x4 + +#define FB_PWRM0_MICB1PU 1 +#define FM_PWRM0_MICB1PU 0x2 + +#define FB_PWRM0_MCLKPEN 0 +#define FM_PWRM0_MCLKPEN 0x1 + +// *** PWRM1 *** +#define FB_PWRM1_SUBPU 7 +#define FM_PWRM1_SUBPU 0x80 + +#define FB_PWRM1_HPLPU 6 +#define FM_PWRM1_HPLPU 0x40 + +#define FB_PWRM1_HPRPU 5 +#define FM_PWRM1_HPRPU 0x20 + +#define FB_PWRM1_SPKLPU 4 +#define FM_PWRM1_SPKLPU 0x10 + +#define FB_PWRM1_SPKRPU 3 +#define FM_PWRM1_SPKRPU 0x8 + +#define FB_PWRM1_D2S2PU 2 +#define FM_PWRM1_D2S2PU 0x4 + +#define FB_PWRM1_D2S1PU 1 +#define FM_PWRM1_D2S1PU 0x2 + +#define FB_PWRM1_VREFPU 0 +#define FM_PWRM1_VREFPU 0x1 + +// *** PWRM2 *** +#define FB_PWRM2_I2S3OPU 5 +#define FM_PWRM2_I2S3OPU 0x20 +#define FV_I2S3OPU_PWR_DOWN 0x0 +#define FV_I2S3OPU_PWR_UP 0x20 + +#define FB_PWRM2_I2S2OPU 4 +#define FM_PWRM2_I2S2OPU 0x10 +#define FV_I2S2OPU_PWR_DOWN 0x0 +#define FV_I2S2OPU_PWR_UP 0x10 + +#define FB_PWRM2_I2S1OPU 3 +#define FM_PWRM2_I2S1OPU 0x8 +#define FV_I2S1OPU_PWR_DOWN 0x0 +#define FV_I2S1OPU_PWR_UP 0x8 + +#define FB_PWRM2_I2S3IPU 2 +#define FM_PWRM2_I2S3IPU 0x4 +#define FV_I2S3IPU_PWR_DOWN 0x0 +#define FV_I2S3IPU_PWR_UP 0x4 + +#define FB_PWRM2_I2S2IPU 1 +#define FM_PWRM2_I2S2IPU 0x2 +#define FV_I2S2IPU_PWR_DOWN 0x0 +#define FV_I2S2IPU_PWR_UP 0x2 + +#define FB_PWRM2_I2S1IPU 0 +#define FM_PWRM2_I2S1IPU 0x1 +#define FV_I2S1IPU_PWR_DOWN 0x0 +#define FV_I2S1IPU_PWR_UP 0x1 + +#define PWRM2_I2SOPU_PWR_DOWN 0x0 +#define PWRM2_I2SOPU_PWR_UP 0x1 +#define PWRM2_I2SIPU_PWR_DOWN 0x0 +#define PWRM2_I2SIPU_PWR_UP 0x1 + +// *** PWRM3 *** +#define FB_PWRM3_BGSBUP 6 +#define FM_PWRM3_BGSBUP 0x40 +#define FV_BGSBUP_ON 0x0 +#define FV_BGSBUP_OFF 0x40 + +#define FB_PWRM3_VGBAPU 5 +#define FM_PWRM3_VGBAPU 0x20 +#define FV_VGBAPU_ON 0x0 +#define FV_VGBAPU_OFF 0x20 + +#define FB_PWRM3_LLINEPU 4 +#define FM_PWRM3_LLINEPU 0x10 + +#define FB_PWRM3_RLINEPU 3 +#define FM_PWRM3_RLINEPU 0x8 + +// *** PWRM4 *** +#define FB_PWRM4_OPSUBPU 4 +#define FM_PWRM4_OPSUBPU 0x10 + +#define FB_PWRM4_OPDACLPU 3 +#define FM_PWRM4_OPDACLPU 0x8 + +#define FB_PWRM4_OPDACRPU 2 +#define FM_PWRM4_OPDACRPU 0x4 + +#define FB_PWRM4_OPSPKLPU 1 +#define FM_PWRM4_OPSPKLPU 0x2 + +#define FB_PWRM4_OPSPKRPU 0 +#define FM_PWRM4_OPSPKRPU 0x1 + +// *** I2SIDCTL *** +#define FB_I2SIDCTL_I2SI3DCTL 4 +#define FM_I2SIDCTL_I2SI3DCTL 0x30 + +#define FB_I2SIDCTL_I2SI2DCTL 2 +#define FM_I2SIDCTL_I2SI2DCTL 0xC + +#define FB_I2SIDCTL_I2SI1DCTL 0 +#define FM_I2SIDCTL_I2SI1DCTL 0x3 + +// *** I2SODCTL *** +#define FB_I2SODCTL_I2SO3DCTL 4 +#define FM_I2SODCTL_I2SO3DCTL 0x30 + +#define FB_I2SODCTL_I2SO2DCTL 2 +#define FM_I2SODCTL_I2SO2DCTL 0xC + +#define FB_I2SODCTL_I2SO1DCTL 0 +#define FM_I2SODCTL_I2SO1DCTL 0x3 + +// *** AUDIOMUX1 *** +#define FB_AUDIOMUX1_ASRCIMUX 6 +#define FM_AUDIOMUX1_ASRCIMUX 0xC0 +#define FV_ASRCIMUX_NONE 0x0 +#define FV_ASRCIMUX_I2S1 0x40 +#define FV_ASRCIMUX_I2S2 0x80 +#define FV_ASRCIMUX_I2S3 0xC0 + +#define FB_AUDIOMUX1_I2S2MUX 3 +#define FM_AUDIOMUX1_I2S2MUX 0x38 +#define FV_I2S2MUX_I2S1 0x0 +#define FV_I2S2MUX_I2S2 0x8 +#define FV_I2S2MUX_I2S3 0x10 +#define FV_I2S2MUX_ADC_DMIC 0x18 +#define FV_I2S2MUX_DMIC2 0x20 +#define FV_I2S2MUX_CLASSD_DSP 0x28 +#define FV_I2S2MUX_DAC_DSP 0x30 +#define FV_I2S2MUX_SUB_DSP 0x38 + +#define FB_AUDIOMUX1_I2S1MUX 0 +#define FM_AUDIOMUX1_I2S1MUX 0x7 +#define FV_I2S1MUX_I2S1 0x0 +#define FV_I2S1MUX_I2S2 0x1 +#define FV_I2S1MUX_I2S3 0x2 +#define FV_I2S1MUX_ADC_DMIC 0x3 +#define FV_I2S1MUX_DMIC2 0x4 +#define FV_I2S1MUX_CLASSD_DSP 0x5 +#define FV_I2S1MUX_DAC_DSP 0x6 +#define FV_I2S1MUX_SUB_DSP 0x7 + +#define AUDIOMUX1_I2SMUX_I2S1 0x0 +#define AUDIOMUX1_I2SMUX_I2S2 0x1 +#define AUDIOMUX1_I2SMUX_I2S3 0x2 +#define AUDIOMUX1_I2SMUX_ADC_DMIC 0x3 +#define AUDIOMUX1_I2SMUX_DMIC2 0x4 +#define AUDIOMUX1_I2SMUX_CLASSD_DSP 0x5 +#define AUDIOMUX1_I2SMUX_DAC_DSP 0x6 +#define AUDIOMUX1_I2SMUX_SUB_DSP 0x7 + +// *** AUDIOMUX2 *** +#define FB_AUDIOMUX2_ASRCOMUX 6 +#define FM_AUDIOMUX2_ASRCOMUX 0xC0 +#define FV_ASRCOMUX_NONE 0x0 +#define FV_ASRCOMUX_I2S1 0x40 +#define FV_ASRCOMUX_I2S2 0x80 +#define FV_ASRCOMUX_I2S3 0xC0 + +#define FB_AUDIOMUX2_DACMUX 3 +#define FM_AUDIOMUX2_DACMUX 0x38 +#define FV_DACMUX_I2S1 0x0 +#define FV_DACMUX_I2S2 0x8 +#define FV_DACMUX_I2S3 0x10 +#define FV_DACMUX_ADC_DMIC 0x18 +#define FV_DACMUX_DMIC2 0x20 +#define FV_DACMUX_CLASSD_DSP 0x28 +#define FV_DACMUX_DAC_DSP 0x30 +#define FV_DACMUX_SUB_DSP 0x38 + +#define FB_AUDIOMUX2_I2S3MUX 0 +#define FM_AUDIOMUX2_I2S3MUX 0x7 +#define FV_I2S3MUX_I2S1 0x0 +#define FV_I2S3MUX_I2S2 0x1 +#define FV_I2S3MUX_I2S3 0x2 +#define FV_I2S3MUX_ADC_DMIC 0x3 +#define FV_I2S3MUX_DMIC2 0x4 +#define FV_I2S3MUX_CLASSD_DSP 0x5 +#define FV_I2S3MUX_DAC_DSP 0x6 +#define FV_I2S3MUX_SUB_DSP 0x7 + +// *** AUDIOMUX3 *** +#define FB_AUDIOMUX3_SUBMUX 3 +#define FM_AUDIOMUX3_SUBMUX 0xF8 +#define FV_SUBMUX_I2S1_L 0x0 +#define FV_SUBMUX_I2S1_R 0x8 +#define FV_SUBMUX_I2S1_LR 0x10 +#define FV_SUBMUX_I2S2_L 0x18 +#define FV_SUBMUX_I2S2_R 0x20 +#define FV_SUBMUX_I2S2_LR 0x28 +#define FV_SUBMUX_I2S3_L 0x30 +#define FV_SUBMUX_I2S3_R 0x38 +#define FV_SUBMUX_I2S3_LR 0x40 +#define FV_SUBMUX_ADC_DMIC_L 0x48 +#define FV_SUBMUX_ADC_DMIC_R 0x50 +#define FV_SUBMUX_ADC_DMIC_LR 0x58 +#define FV_SUBMUX_DMIC_L 0x60 +#define FV_SUBMUX_DMIC_R 0x68 +#define FV_SUBMUX_DMIC_LR 0x70 +#define FV_SUBMUX_CLASSD_DSP_L 0x78 +#define FV_SUBMUX_CLASSD_DSP_R 0x80 +#define FV_SUBMUX_CLASSD_DSP_LR 0x88 + +#define FB_AUDIOMUX3_CLSSDMUX 0 +#define FM_AUDIOMUX3_CLSSDMUX 0x7 +#define FV_CLSSDMUX_I2S1 0x0 +#define FV_CLSSDMUX_I2S2 0x1 +#define FV_CLSSDMUX_I2S3 0x2 +#define FV_CLSSDMUX_ADC_DMIC 0x3 +#define FV_CLSSDMUX_DMIC2 0x4 +#define FV_CLSSDMUX_CLASSD_DSP 0x5 +#define FV_CLSSDMUX_DAC_DSP 0x6 +#define FV_CLSSDMUX_SUB_DSP 0x7 + +// *** HSDCTL1 *** +#define FB_HSDCTL1_HPJKTYPE 7 +#define FM_HSDCTL1_HPJKTYPE 0x80 + +#define FB_HSDCTL1_CON_DET_PWD 6 +#define FM_HSDCTL1_CON_DET_PWD 0x40 + +#define FB_HSDCTL1_DETCYC 4 +#define FM_HSDCTL1_DETCYC 0x30 + +#define FB_HSDCTL1_HPDLYBYP 3 +#define FM_HSDCTL1_HPDLYBYP 0x8 + +#define FB_HSDCTL1_HSDETPOL 2 +#define FM_HSDCTL1_HSDETPOL 0x4 + +#define FB_HSDCTL1_HPID_EN 1 +#define FM_HSDCTL1_HPID_EN 0x2 + +#define FB_HSDCTL1_GBLHS_EN 0 +#define FM_HSDCTL1_GBLHS_EN 0x1 + +// *** HSDCTL2 *** +#define FB_HSDCTL2_FMICBIAS1 6 +#define FM_HSDCTL2_FMICBIAS1 0xC0 + +#define FB_HSDCTL2_MB1MODE 5 +#define FM_HSDCTL2_MB1MODE 0x20 +#define FV_MB1MODE_AUTO 0x0 +#define FV_MB1MODE_MANUAL 0x20 + +#define FB_HSDCTL2_FORCETRG 4 +#define FM_HSDCTL2_FORCETRG 0x10 + +#define FB_HSDCTL2_SWMODE 3 +#define FM_HSDCTL2_SWMODE 0x8 + +#define FB_HSDCTL2_GHSHIZ 2 +#define FM_HSDCTL2_GHSHIZ 0x4 + +#define FB_HSDCTL2_FPLUGTYPE 0 +#define FM_HSDCTL2_FPLUGTYPE 0x3 + +// *** HSDSTAT *** +#define FB_HSDSTAT_MBIAS1DRV 5 +#define FM_HSDSTAT_MBIAS1DRV 0x60 + +#define FB_HSDSTAT_HSDETSTAT 3 +#define FM_HSDSTAT_HSDETSTAT 0x8 + +#define FB_HSDSTAT_PLUGTYPE 1 +#define FM_HSDSTAT_PLUGTYPE 0x6 + +#define FB_HSDSTAT_HSDETDONE 0 +#define FM_HSDSTAT_HSDETDONE 0x1 + +// *** HSDDELAY *** +#define FB_HSDDELAY_T_STABLE 0 +#define FM_HSDDELAY_T_STABLE 0x7 + +// *** BUTCTL *** +#define FB_BUTCTL_BPUSHSTAT 7 +#define FM_BUTCTL_BPUSHSTAT 0x80 + +#define FB_BUTCTL_BPUSHDET 6 +#define FM_BUTCTL_BPUSHDET 0x40 + +#define FB_BUTCTL_BPUSHEN 5 +#define FM_BUTCTL_BPUSHEN 0x20 + +#define FB_BUTCTL_BSTABLE_L 3 +#define FM_BUTCTL_BSTABLE_L 0x18 + +#define FB_BUTCTL_BSTABLE_S 0 +#define FM_BUTCTL_BSTABLE_S 0x7 + +// *** CH0AIC *** +#define FB_CH0AIC_INSELL 6 +#define FM_CH0AIC_INSELL 0xC0 + +#define FB_CH0AIC_MICBST0 4 +#define FM_CH0AIC_MICBST0 0x30 + +#define FB_CH0AIC_LADCIN 2 +#define FM_CH0AIC_LADCIN 0xC + +#define FB_CH0AIC_IN_BYPS_L_SEL 1 +#define FM_CH0AIC_IN_BYPS_L_SEL 0x2 + +#define FB_CH0AIC_IPCH0S 0 +#define FM_CH0AIC_IPCH0S 0x1 + +// *** CH1AIC *** +#define FB_CH1AIC_INSELR 6 +#define FM_CH1AIC_INSELR 0xC0 + +#define FB_CH1AIC_MICBST1 4 +#define FM_CH1AIC_MICBST1 0x30 + +#define FB_CH1AIC_RADCIN 2 +#define FM_CH1AIC_RADCIN 0xC + +#define FB_CH1AIC_IN_BYPS_R_SEL 1 +#define FM_CH1AIC_IN_BYPS_R_SEL 0x2 + +#define FB_CH1AIC_IPCH1S 0 +#define FM_CH1AIC_IPCH1S 0x1 + +// *** ICTL0 *** +#define FB_ICTL0_IN1POL 7 +#define FM_ICTL0_IN1POL 0x80 + +#define FB_ICTL0_IN0POL 6 +#define FM_ICTL0_IN0POL 0x40 + +#define FB_ICTL0_INPCH10SEL 4 +#define FM_ICTL0_INPCH10SEL 0x30 + +#define FB_ICTL0_IN1MUTE 3 +#define FM_ICTL0_IN1MUTE 0x8 + +#define FB_ICTL0_IN0MUTE 2 +#define FM_ICTL0_IN0MUTE 0x4 + +#define FB_ICTL0_IN1HP 1 +#define FM_ICTL0_IN1HP 0x2 + +#define FB_ICTL0_IN0HP 0 +#define FM_ICTL0_IN0HP 0x1 + +// *** ICTL1 *** +#define FB_ICTL1_IN3POL 7 +#define FM_ICTL1_IN3POL 0x80 + +#define FB_ICTL1_IN2POL 6 +#define FM_ICTL1_IN2POL 0x40 + +#define FB_ICTL1_INPCH32SEL 4 +#define FM_ICTL1_INPCH32SEL 0x30 + +#define FB_ICTL1_IN3MUTE 3 +#define FM_ICTL1_IN3MUTE 0x8 + +#define FB_ICTL1_IN2MUTE 2 +#define FM_ICTL1_IN2MUTE 0x4 + +#define FB_ICTL1_IN3HP 1 +#define FM_ICTL1_IN3HP 0x2 + +#define FB_ICTL1_IN2HP 0 +#define FM_ICTL1_IN2HP 0x1 + +// *** MICBIAS *** +#define FB_MICBIAS_MICBOV2 4 +#define FM_MICBIAS_MICBOV2 0x30 + +#define FB_MICBIAS_MICBOV1 6 +#define FM_MICBIAS_MICBOV1 0xC0 + +#define FB_MICBIAS_SPARE1 2 +#define FM_MICBIAS_SPARE1 0xC + +#define FB_MICBIAS_SPARE2 0 +#define FM_MICBIAS_SPARE2 0x3 + +// *** PGAZ *** +#define FB_PGAZ_INHPOR 1 +#define FM_PGAZ_INHPOR 0x2 + +#define FB_PGAZ_TOEN 0 +#define FM_PGAZ_TOEN 0x1 + +// *** ASRCILVOL *** +#define FB_ASRCILVOL_ASRCILVOL 0 +#define FM_ASRCILVOL_ASRCILVOL 0xFF + +// *** ASRCIRVOL *** +#define FB_ASRCIRVOL_ASRCIRVOL 0 +#define FM_ASRCIRVOL_ASRCIRVOL 0xFF + +// *** ASRCOLVOL *** +#define FB_ASRCOLVOL_ASRCOLVOL 0 +#define FM_ASRCOLVOL_ASRCOLVOL 0xFF + +// *** ASRCORVOL *** +#define FB_ASRCORVOL_ASRCOLVOL 0 +#define FM_ASRCORVOL_ASRCOLVOL 0xFF + +// *** IVOLCTLU *** +#define FB_IVOLCTLU_IFADE 3 +#define FM_IVOLCTLU_IFADE 0x8 + +#define FB_IVOLCTLU_INPVOLU 2 +#define FM_IVOLCTLU_INPVOLU 0x4 + +#define FB_IVOLCTLU_PGAVOLU 1 +#define FM_IVOLCTLU_PGAVOLU 0x2 + +#define FB_IVOLCTLU_ASRCVOLU 0 +#define FM_IVOLCTLU_ASRCVOLU 0x1 + +// *** ALCCTL0 *** +#define FB_ALCCTL0_ALCMODE 7 +#define FM_ALCCTL0_ALCMODE 0x80 + +#define FB_ALCCTL0_ALCREF 4 +#define FM_ALCCTL0_ALCREF 0x70 + +#define FB_ALCCTL0_ALCEN3 3 +#define FM_ALCCTL0_ALCEN3 0x8 + +#define FB_ALCCTL0_ALCEN2 2 +#define FM_ALCCTL0_ALCEN2 0x4 + +#define FB_ALCCTL0_ALCEN1 1 +#define FM_ALCCTL0_ALCEN1 0x2 + +#define FB_ALCCTL0_ALCEN0 0 +#define FM_ALCCTL0_ALCEN0 0x1 + +// *** ALCCTL1 *** +#define FB_ALCCTL1_MAXGAIN 4 +#define FM_ALCCTL1_MAXGAIN 0x70 + +#define FB_ALCCTL1_ALCL 0 +#define FM_ALCCTL1_ALCL 0xF + +// *** ALCCTL2 *** +#define FB_ALCCTL2_ALCZC 7 +#define FM_ALCCTL2_ALCZC 0x80 + +#define FB_ALCCTL2_MINGAIN 4 +#define FM_ALCCTL2_MINGAIN 0x70 + +#define FB_ALCCTL2_HLD 0 +#define FM_ALCCTL2_HLD 0xF + +// *** ALCCTL3 *** +#define FB_ALCCTL3_DCY 4 +#define FM_ALCCTL3_DCY 0xF0 + +#define FB_ALCCTL3_ATK 0 +#define FM_ALCCTL3_ATK 0xF + +// *** NGATE *** +#define FB_NGATE_NGTH 3 +#define FM_NGATE_NGTH 0xF8 + +#define FB_NGATE_NGG 1 +#define FM_NGATE_NGG 0x6 + +#define FB_NGATE_NGAT 0 +#define FM_NGATE_NGAT 0x1 + +// *** DMICCTL *** +#define FB_DMICCTL_DMIC2EN 7 +#define FM_DMICCTL_DMIC2EN 0x80 + +#define FB_DMICCTL_DMIC1EN 6 +#define FM_DMICCTL_DMIC1EN 0x40 + +#define FB_DMICCTL_DMONO 4 +#define FM_DMICCTL_DMONO 0x10 + +#define FB_DMICCTL_DMDCLK 2 +#define FM_DMICCTL_DMDCLK 0xC + +#define FB_DMICCTL_DMRATE 0 +#define FM_DMICCTL_DMRATE 0x3 + +// *** DACCTL *** +#define FB_DACCTL_DACPOLR 7 +#define FM_DACCTL_DACPOLR 0x80 +#define FV_DACPOLR_NORMAL 0x0 +#define FV_DACPOLR_INVERTED 0x80 + +#define FB_DACCTL_DACPOLL 6 +#define FM_DACCTL_DACPOLL 0x40 +#define FV_DACPOLL_NORMAL 0x0 +#define FV_DACPOLL_INVERTED 0x40 + +#define FB_DACCTL_DACDITH 4 +#define FM_DACCTL_DACDITH 0x30 +#define FV_DACDITH_DYNAMIC_HALF 0x0 +#define FV_DACDITH_DYNAMIC_FULL 0x10 +#define FV_DACDITH_DISABLED 0x20 +#define FV_DACDITH_STATIC 0x30 + +#define FB_DACCTL_DACMUTE 3 +#define FM_DACCTL_DACMUTE 0x8 +#define FV_DACMUTE_ENABLE 0x8 +#define FV_DACMUTE_DISABLE 0x0 + +#define FB_DACCTL_DACDEM 2 +#define FM_DACCTL_DACDEM 0x4 +#define FV_DACDEM_ENABLE 0x4 +#define FV_DACDEM_DISABLE 0x0 + +#define FB_DACCTL_ABYPASS 0 +#define FM_DACCTL_ABYPASS 0x1 + +// *** SPKCTL *** +#define FB_SPKCTL_SPKPOLR 7 +#define FM_SPKCTL_SPKPOLR 0x80 +#define FV_SPKPOLR_NORMAL 0x0 +#define FV_SPKPOLR_INVERTED 0x80 + +#define FB_SPKCTL_SPKPOLL 6 +#define FM_SPKCTL_SPKPOLL 0x40 +#define FV_SPKPOLL_NORMAL 0x0 +#define FV_SPKPOLL_INVERTED 0x40 + +#define FB_SPKCTL_SPKMUTE 3 +#define FM_SPKCTL_SPKMUTE 0x8 +#define FV_SPKMUTE_ENABLE 0x8 +#define FV_SPKMUTE_DISABLE 0x0 + +#define FB_SPKCTL_SPKDEM 2 +#define FM_SPKCTL_SPKDEM 0x4 +#define FV_SPKDEM_ENABLE 0x4 +#define FV_SPKDEM_DISABLE 0x0 + +// *** SUBCTL *** +#define FB_SUBCTL_SUBPOL 7 +#define FM_SUBCTL_SUBPOL 0x80 + +#define FB_SUBCTL_SUBMUTE 3 +#define FM_SUBCTL_SUBMUTE 0x8 + +#define FB_SUBCTL_SUBDEM 2 +#define FM_SUBCTL_SUBDEM 0x4 + +#define FB_SUBCTL_SUBMUX 1 +#define FM_SUBCTL_SUBMUX 0x2 + +#define FB_SUBCTL_SUBILMDIS 0 +#define FM_SUBCTL_SUBILMDIS 0x1 + +// *** DCCTL *** +#define FB_DCCTL_SUBDCBYP 7 +#define FM_DCCTL_SUBDCBYP 0x80 + +#define FB_DCCTL_DACDCBYP 6 +#define FM_DCCTL_DACDCBYP 0x40 + +#define FB_DCCTL_SPKDCBYP 5 +#define FM_DCCTL_SPKDCBYP 0x20 + +#define FB_DCCTL_DCCOEFSEL 0 +#define FM_DCCTL_DCCOEFSEL 0x7 + +// *** OVOLCTLU *** +#define FB_OVOLCTLU_OFADE 4 +#define FM_OVOLCTLU_OFADE 0x10 + +#define FB_OVOLCTLU_SUBVOLU 3 +#define FM_OVOLCTLU_SUBVOLU 0x8 + +#define FB_OVOLCTLU_MVOLU 2 +#define FM_OVOLCTLU_MVOLU 0x4 + +#define FB_OVOLCTLU_SPKVOLU 1 +#define FM_OVOLCTLU_SPKVOLU 0x2 + +#define FB_OVOLCTLU_HPVOLU 0 +#define FM_OVOLCTLU_HPVOLU 0x1 + +// *** MUTEC *** +#define FB_MUTEC_ZDSTAT 7 +#define FM_MUTEC_ZDSTAT 0x80 + +#define FB_MUTEC_ZDLEN 4 +#define FM_MUTEC_ZDLEN 0x30 + +#define FB_MUTEC_APWD 3 +#define FM_MUTEC_APWD 0x8 + +#define FB_MUTEC_AMUTE 2 +#define FM_MUTEC_AMUTE 0x4 + +// *** MVOLL *** +#define FB_MVOLL_MVOL_L 0 +#define FM_MVOLL_MVOL_L 0xFF + +// *** MVOLR *** +#define FB_MVOLR_MVOL_R 0 +#define FM_MVOLR_MVOL_R 0xFF + +// *** HPVOLL *** +#define FB_HPVOLL_HPVOL_L 0 +#define FM_HPVOLL_HPVOL_L 0x7F + +// *** HPVOLR *** +#define FB_HPVOLR_HPVOL_R 0 +#define FM_HPVOLR_HPVOL_R 0x7F + +// *** SPKVOLL *** +#define FB_SPKVOLL_SPKVOL_L 0 +#define FM_SPKVOLL_SPKVOL_L 0x7F + +// *** SPKVOLR *** +#define FB_SPKVOLR_SPKVOL_R 0 +#define FM_SPKVOLR_SPKVOL_R 0x7F + +// *** SUBVOL *** +#define FB_SUBVOL_SUBVOL 0 +#define FM_SUBVOL_SUBVOL 0x7F + +// *** COP0 *** +#define FB_COP0_COPATTEN 7 +#define FM_COP0_COPATTEN 0x80 + +#define FB_COP0_COPGAIN 6 +#define FM_COP0_COPGAIN 0x40 + +#define FB_COP0_HDELTAEN 5 +#define FM_COP0_HDELTAEN 0x20 + +#define FB_COP0_COPTARGET 0 +#define FM_COP0_COPTARGET 0x1F + +// *** COP1 *** +#define FB_COP1_HDCOMPMODE 6 +#define FM_COP1_HDCOMPMODE 0x40 + +#define FB_COP1_AVGLENGTH 2 +#define FM_COP1_AVGLENGTH 0x3C + +#define FB_COP1_MONRATE 0 +#define FM_COP1_MONRATE 0x3 + +// *** COPSTAT *** +#define FB_COPSTAT_HDELTADET 7 +#define FM_COPSTAT_HDELTADET 0x80 + +#define FB_COPSTAT_UV 6 +#define FM_COPSTAT_UV 0x40 + +#define FB_COPSTAT_COPADJ 0 +#define FM_COPSTAT_COPADJ 0x3F + +// *** PWM0 *** +#define FB_PWM0_SCTO 6 +#define FM_PWM0_SCTO 0xC0 + +#define FB_PWM0_UVLO 5 +#define FM_PWM0_UVLO 0x20 + +#define FB_PWM0_BFDIS 3 +#define FM_PWM0_BFDIS 0x8 + +#define FB_PWM0_PWMMODE 2 +#define FM_PWM0_PWMMODE 0x4 + +#define FB_PWM0_NOOFFSET 0 +#define FM_PWM0_NOOFFSET 0x1 + +// *** PWM1 *** +#define FB_PWM1_DITHPOS 4 +#define FM_PWM1_DITHPOS 0x70 + +#define FB_PWM1_DYNDITH 1 +#define FM_PWM1_DYNDITH 0x2 + +#define FB_PWM1_DITHDIS 0 +#define FM_PWM1_DITHDIS 0x1 + +// *** PWM2 *** +// *** PWM3 *** +#define FB_PWM3_PWMMUX 6 +#define FM_PWM3_PWMMUX 0xC0 + +#define FB_PWM3_CVALUE 0 +#define FM_PWM3_CVALUE 0x7 + +// *** HPSW *** +#define FB_HPSW_HPDETSTATE 4 +#define FM_HPSW_HPDETSTATE 0x10 + +#define FB_HPSW_HPSWEN 2 +#define FM_HPSW_HPSWEN 0xC + +#define FB_HPSW_HPSWPOL 1 +#define FM_HPSW_HPSWPOL 0x2 + +#define FB_HPSW_TSDEN 0 +#define FM_HPSW_TSDEN 0x1 + +// *** THERMTS *** +#define FB_THERMTS_TRIPHS 7 +#define FM_THERMTS_TRIPHS 0x80 + +#define FB_THERMTS_TRIPLS 6 +#define FM_THERMTS_TRIPLS 0x40 + +#define FB_THERMTS_TRIPSPLIT 4 +#define FM_THERMTS_TRIPSPLIT 0x30 + +#define FB_THERMTS_TRIPSHIFT 2 +#define FM_THERMTS_TRIPSHIFT 0xC + +#define FB_THERMTS_TSPOLL 0 +#define FM_THERMTS_TSPOLL 0x3 + +// *** THERMSPK1 *** +#define FB_THERMSPK1_FORCEPWD 7 +#define FM_THERMSPK1_FORCEPWD 0x80 + +#define FB_THERMSPK1_INSTCUTMODE 6 +#define FM_THERMSPK1_INSTCUTMODE 0x40 + +#define FB_THERMSPK1_INCRATIO 4 +#define FM_THERMSPK1_INCRATIO 0x30 + +#define FB_THERMSPK1_INCSTEP 2 +#define FM_THERMSPK1_INCSTEP 0xC + +#define FB_THERMSPK1_DECSTEP 0 +#define FM_THERMSPK1_DECSTEP 0x3 + +// *** THERMSTAT *** +#define FB_THERMSTAT_FPWDS 7 +#define FM_THERMSTAT_FPWDS 0x80 + +#define FB_THERMSTAT_VOLSTAT 0 +#define FM_THERMSTAT_VOLSTAT 0x7F + +// *** SCSTAT *** +#define FB_SCSTAT_ESDF 3 +#define FM_SCSTAT_ESDF 0x18 + +#define FB_SCSTAT_CPF 2 +#define FM_SCSTAT_CPF 0x4 + +#define FB_SCSTAT_CLSDF 0 +#define FM_SCSTAT_CLSDF 0x3 + +// *** SDMON *** +#define FB_SDMON_SDFORCE 7 +#define FM_SDMON_SDFORCE 0x80 + +#define FB_SDMON_SDVALUE 0 +#define FM_SDMON_SDVALUE 0x1F + +// *** SPKEQFILT *** +#define FB_SPKEQFILT_EQ2EN 7 +#define FM_SPKEQFILT_EQ2EN 0x80 +#define FV_EQ2EN_ENABLE 0x80 +#define FV_EQ2EN_DISABLE 0x0 + +#define FB_SPKEQFILT_EQ2BE 4 +#define FM_SPKEQFILT_EQ2BE 0x70 + +#define FB_SPKEQFILT_EQ1EN 3 +#define FM_SPKEQFILT_EQ1EN 0x8 +#define FV_EQ1EN_ENABLE 0x8 +#define FV_EQ1EN_DISABLE 0x0 + +#define FB_SPKEQFILT_EQ1BE 0 +#define FM_SPKEQFILT_EQ1BE 0x7 + +#define SPKEQFILT_EQEN_ENABLE 0x1 +#define SPKEQFILT_EQEN_DISABLE 0x0 + +// *** SPKCRWDL *** +#define FB_SPKCRWDL_WDATA_L 0 +#define FM_SPKCRWDL_WDATA_L 0xFF + +// *** SPKCRWDM *** +#define FB_SPKCRWDM_WDATA_M 0 +#define FM_SPKCRWDM_WDATA_M 0xFF + +// *** SPKCRWDH *** +#define FB_SPKCRWDH_WDATA_H 0 +#define FM_SPKCRWDH_WDATA_H 0xFF + +// *** SPKCRRDL *** +#define FB_SPKCRRDL_RDATA_L 0 +#define FM_SPKCRRDL_RDATA_L 0xFF + +// *** SPKCRRDM *** +#define FB_SPKCRRDM_RDATA_M 0 +#define FM_SPKCRRDM_RDATA_M 0xFF + +// *** SPKCRRDH *** +#define FB_SPKCRRDH_RDATA_H 0 +#define FM_SPKCRRDH_RDATA_H 0xFF + +// *** SPKCRADD *** +#define FB_SPKCRADD_ADDRESS 0 +#define FM_SPKCRADD_ADDRESS 0xFF + +// *** SPKCRS *** +#define FB_SPKCRS_ACCSTAT 7 +#define FM_SPKCRS_ACCSTAT 0x80 + +// *** SPKMBCEN *** +#define FB_SPKMBCEN_MBCEN3 2 +#define FM_SPKMBCEN_MBCEN3 0x4 +#define FV_MBCEN3_ENABLE 0x4 +#define FV_MBCEN3_DISABLE 0x0 + +#define FB_SPKMBCEN_MBCEN2 1 +#define FM_SPKMBCEN_MBCEN2 0x2 +#define FV_MBCEN2_ENABLE 0x2 +#define FV_MBCEN2_DISABLE 0x0 + +#define FB_SPKMBCEN_MBCEN1 0 +#define FM_SPKMBCEN_MBCEN1 0x1 +#define FV_MBCEN1_ENABLE 0x1 +#define FV_MBCEN1_DISABLE 0x0 + +#define SPKMBCEN_MBCEN_ENABLE 0x1 +#define SPKMBCEN_MBCEN_DISABLE 0x0 + +// *** SPKMBCCTL *** +#define FB_SPKMBCCTL_LVLMODE3 5 +#define FM_SPKMBCCTL_LVLMODE3 0x20 + +#define FB_SPKMBCCTL_WINSEL3 4 +#define FM_SPKMBCCTL_WINSEL3 0x10 + +#define FB_SPKMBCCTL_LVLMODE2 3 +#define FM_SPKMBCCTL_LVLMODE2 0x8 + +#define FB_SPKMBCCTL_WINSEL2 2 +#define FM_SPKMBCCTL_WINSEL2 0x4 + +#define FB_SPKMBCCTL_LVLMODE1 1 +#define FM_SPKMBCCTL_LVLMODE1 0x2 + +#define FB_SPKMBCCTL_WINSEL1 0 +#define FM_SPKMBCCTL_WINSEL1 0x1 + +// *** SPKCLECTL *** +#define FB_SPKCLECTL_LVLMODE 4 +#define FM_SPKCLECTL_LVLMODE 0x10 + +#define FB_SPKCLECTL_WINSEL 3 +#define FM_SPKCLECTL_WINSEL 0x8 + +#define FB_SPKCLECTL_EXPEN 2 +#define FM_SPKCLECTL_EXPEN 0x4 +#define FV_EXPEN_ENABLE 0x4 +#define FV_EXPEN_DISABLE 0x0 + +#define FB_SPKCLECTL_LIMEN 1 +#define FM_SPKCLECTL_LIMEN 0x2 +#define FV_LIMEN_ENABLE 0x2 +#define FV_LIMEN_DISABLE 0x0 + +#define FB_SPKCLECTL_COMPEN 0 +#define FM_SPKCLECTL_COMPEN 0x1 +#define FV_COMPEN_ENABLE 0x1 +#define FV_COMPEN_DISABLE 0x0 + +// *** SPKCLEMUG *** +#define FB_SPKCLEMUG_MUGAIN 0 +#define FM_SPKCLEMUG_MUGAIN 0x1F + +// *** SPKCOMPTHR *** +#define FB_SPKCOMPTHR_THRESH 0 +#define FM_SPKCOMPTHR_THRESH 0xFF + +// *** SPKCOMPRAT *** +#define FB_SPKCOMPRAT_RATIO 0 +#define FM_SPKCOMPRAT_RATIO 0x1F + +// *** SPKCOMPATKL *** +#define FB_SPKCOMPATKL_TCATKL 0 +#define FM_SPKCOMPATKL_TCATKL 0xFF + +// *** SPKCOMPATKH *** +#define FB_SPKCOMPATKH_TCATKH 0 +#define FM_SPKCOMPATKH_TCATKH 0xFF + +// *** SPKCOMPRELL *** +#define FB_SPKCOMPRELL_TCRELL 0 +#define FM_SPKCOMPRELL_TCRELL 0xFF + +// *** SPKCOMPRELH *** +#define FB_SPKCOMPRELH_TCRELH 0 +#define FM_SPKCOMPRELH_TCRELH 0xFF + +// *** SPKLIMTHR *** +#define FB_SPKLIMTHR_THRESH 0 +#define FM_SPKLIMTHR_THRESH 0xFF + +// *** SPKLIMTGT *** +#define FB_SPKLIMTGT_TARGET 0 +#define FM_SPKLIMTGT_TARGET 0xFF + +// *** SPKLIMATKL *** +#define FB_SPKLIMATKL_TCATKL 0 +#define FM_SPKLIMATKL_TCATKL 0xFF + +// *** SPKLIMATKH *** +#define FB_SPKLIMATKH_TCATKH 0 +#define FM_SPKLIMATKH_TCATKH 0xFF + +// *** SPKLIMRELL *** +#define FB_SPKLIMRELL_TCRELL 0 +#define FM_SPKLIMRELL_TCRELL 0xFF + +// *** SPKLIMRELH *** +#define FB_SPKLIMRELH_TCRELH 0 +#define FM_SPKLIMRELH_TCRELH 0xFF + +// *** SPKEXPTHR *** +#define FB_SPKEXPTHR_THRESH 0 +#define FM_SPKEXPTHR_THRESH 0xFF + +// *** SPKEXPRAT *** +#define FB_SPKEXPRAT_RATIO 0 +#define FM_SPKEXPRAT_RATIO 0x7 + +// *** SPKEXPATKL *** +#define FB_SPKEXPATKL_TCATKL 0 +#define FM_SPKEXPATKL_TCATKL 0xFF + +// *** SPKEXPATKH *** +#define FB_SPKEXPATKH_TCATKH 0 +#define FM_SPKEXPATKH_TCATKH 0xFF + +// *** SPKEXPRELL *** +#define FB_SPKEXPRELL_TCRELL 0 +#define FM_SPKEXPRELL_TCRELL 0xFF + +// *** SPKEXPRELH *** +#define FB_SPKEXPRELH_TCRELH 0 +#define FM_SPKEXPRELH_TCRELH 0xFF + +// *** SPKFXCTL *** +#define FB_SPKFXCTL_3DEN 4 +#define FM_SPKFXCTL_3DEN 0x10 + +#define FB_SPKFXCTL_TEEN 3 +#define FM_SPKFXCTL_TEEN 0x8 + +#define FB_SPKFXCTL_TNLFBYP 2 +#define FM_SPKFXCTL_TNLFBYP 0x4 + +#define FB_SPKFXCTL_BEEN 1 +#define FM_SPKFXCTL_BEEN 0x2 + +#define FB_SPKFXCTL_BNLFBYP 0 +#define FM_SPKFXCTL_BNLFBYP 0x1 + +// *** DACEQFILT *** +#define FB_DACEQFILT_EQ2EN 7 +#define FM_DACEQFILT_EQ2EN 0x80 +#define FV_EQ2EN_ENABLE 0x80 +#define FV_EQ2EN_DISABLE 0x0 + +#define FB_DACEQFILT_EQ2BE 4 +#define FM_DACEQFILT_EQ2BE 0x70 + +#define FB_DACEQFILT_EQ1EN 3 +#define FM_DACEQFILT_EQ1EN 0x8 +#define FV_EQ1EN_ENABLE 0x8 +#define FV_EQ1EN_DISABLE 0x0 + +#define FB_DACEQFILT_EQ1BE 0 +#define FM_DACEQFILT_EQ1BE 0x7 + +#define DACEQFILT_EQEN_ENABLE 0x1 +#define DACEQFILT_EQEN_DISABLE 0x0 + +// *** DACCRWDL *** +#define FB_DACCRWDL_WDATA_L 0 +#define FM_DACCRWDL_WDATA_L 0xFF + +// *** DACCRWDM *** +#define FB_DACCRWDM_WDATA_M 0 +#define FM_DACCRWDM_WDATA_M 0xFF + +// *** DACCRWDH *** +#define FB_DACCRWDH_WDATA_H 0 +#define FM_DACCRWDH_WDATA_H 0xFF + +// *** DACCRRDL *** +#define FB_DACCRRDL_RDATA_L 0 +#define FM_DACCRRDL_RDATA_L 0xFF + +// *** DACCRRDM *** +#define FB_DACCRRDM_RDATA_M 0 +#define FM_DACCRRDM_RDATA_M 0xFF + +// *** DACCRRDH *** +#define FB_DACCRRDH_RDATA_H 0 +#define FM_DACCRRDH_RDATA_H 0xFF + +// *** DACCRADD *** +#define FB_DACCRADD_ADDRESS 0 +#define FM_DACCRADD_ADDRESS 0xFF + +// *** DACCRS *** +#define FB_DACCRS_ACCSTAT 7 +#define FM_DACCRS_ACCSTAT 0x80 + +// *** DACMBCEN *** +#define FB_DACMBCEN_MBCEN3 2 +#define FM_DACMBCEN_MBCEN3 0x4 +#define FV_MBCEN3_ENABLE 0x4 +#define FV_MBCEN3_DISABLE 0x0 + +#define FB_DACMBCEN_MBCEN2 1 +#define FM_DACMBCEN_MBCEN2 0x2 +#define FV_MBCEN2_ENABLE 0x2 +#define FV_MBCEN2_DISABLE 0x0 + +#define FB_DACMBCEN_MBCEN1 0 +#define FM_DACMBCEN_MBCEN1 0x1 +#define FV_MBCEN1_ENABLE 0x1 +#define FV_MBCEN1_DISABLE 0x0 + +#define DACMBCEN_MBCEN_ENABLE 0x1 +#define DACMBCEN_MBCEN_DISABLE 0x0 + +// *** DACMBCCTL *** +#define FB_DACMBCCTL_LVLMODE3 5 +#define FM_DACMBCCTL_LVLMODE3 0x20 + +#define FB_DACMBCCTL_WINSEL3 4 +#define FM_DACMBCCTL_WINSEL3 0x10 + +#define FB_DACMBCCTL_LVLMODE2 3 +#define FM_DACMBCCTL_LVLMODE2 0x8 + +#define FB_DACMBCCTL_WINSEL2 2 +#define FM_DACMBCCTL_WINSEL2 0x4 + +#define FB_DACMBCCTL_LVLMODE1 1 +#define FM_DACMBCCTL_LVLMODE1 0x2 + +#define FB_DACMBCCTL_WINSEL1 0 +#define FM_DACMBCCTL_WINSEL1 0x1 + +// *** DACCLECTL *** +#define FB_DACCLECTL_LVLMODE 4 +#define FM_DACCLECTL_LVLMODE 0x10 + +#define FB_DACCLECTL_WINSEL 3 +#define FM_DACCLECTL_WINSEL 0x8 + +#define FB_DACCLECTL_EXPEN 2 +#define FM_DACCLECTL_EXPEN 0x4 +#define FV_EXPEN_ENABLE 0x4 +#define FV_EXPEN_DISABLE 0x0 + +#define FB_DACCLECTL_LIMEN 1 +#define FM_DACCLECTL_LIMEN 0x2 +#define FV_LIMEN_ENABLE 0x2 +#define FV_LIMEN_DISABLE 0x0 + +#define FB_DACCLECTL_COMPEN 0 +#define FM_DACCLECTL_COMPEN 0x1 +#define FV_COMPEN_ENABLE 0x1 +#define FV_COMPEN_DISABLE 0x0 + +// *** DACCLEMUG *** +#define FB_DACCLEMUG_MUGAIN 0 +#define FM_DACCLEMUG_MUGAIN 0x1F + +// *** DACCOMPTHR *** +#define FB_DACCOMPTHR_THRESH 0 +#define FM_DACCOMPTHR_THRESH 0xFF + +// *** DACCOMPRAT *** +#define FB_DACCOMPRAT_RATIO 0 +#define FM_DACCOMPRAT_RATIO 0x1F + +// *** DACCOMPATKL *** +#define FB_DACCOMPATKL_TCATKL 0 +#define FM_DACCOMPATKL_TCATKL 0xFF + +// *** DACCOMPATKH *** +#define FB_DACCOMPATKH_TCATKH 0 +#define FM_DACCOMPATKH_TCATKH 0xFF + +// *** DACCOMPRELL *** +#define FB_DACCOMPRELL_TCRELL 0 +#define FM_DACCOMPRELL_TCRELL 0xFF + +// *** DACCOMPRELH *** +#define FB_DACCOMPRELH_TCRELH 0 +#define FM_DACCOMPRELH_TCRELH 0xFF + +// *** DACLIMTHR *** +#define FB_DACLIMTHR_THRESH 0 +#define FM_DACLIMTHR_THRESH 0xFF + +// *** DACLIMTGT *** +#define FB_DACLIMTGT_TARGET 0 +#define FM_DACLIMTGT_TARGET 0xFF + +// *** DACLIMATKL *** +#define FB_DACLIMATKL_TCATKL 0 +#define FM_DACLIMATKL_TCATKL 0xFF + +// *** DACLIMATKH *** +#define FB_DACLIMATKH_TCATKH 0 +#define FM_DACLIMATKH_TCATKH 0xFF + +// *** DACLIMRELL *** +#define FB_DACLIMRELL_TCRELL 0 +#define FM_DACLIMRELL_TCRELL 0xFF + +// *** DACLIMRELH *** +#define FB_DACLIMRELH_TCRELH 0 +#define FM_DACLIMRELH_TCRELH 0xFF + +// *** DACEXPTHR *** +#define FB_DACEXPTHR_THRESH 0 +#define FM_DACEXPTHR_THRESH 0xFF + +// *** DACEXPRAT *** +#define FB_DACEXPRAT_RATIO 0 +#define FM_DACEXPRAT_RATIO 0x7 + +// *** DACEXPATKL *** +#define FB_DACEXPATKL_TCATKL 0 +#define FM_DACEXPATKL_TCATKL 0xFF + +// *** DACEXPATKH *** +#define FB_DACEXPATKH_TCATKH 0 +#define FM_DACEXPATKH_TCATKH 0xFF + +// *** DACEXPRELL *** +#define FB_DACEXPRELL_TCRELL 0 +#define FM_DACEXPRELL_TCRELL 0xFF + +// *** DACEXPRELH *** +#define FB_DACEXPRELH_TCRELH 0 +#define FM_DACEXPRELH_TCRELH 0xFF + +// *** DACFXCTL *** +#define FB_DACFXCTL_3DEN 4 +#define FM_DACFXCTL_3DEN 0x10 + +#define FB_DACFXCTL_TEEN 3 +#define FM_DACFXCTL_TEEN 0x8 + +#define FB_DACFXCTL_TNLFBYP 2 +#define FM_DACFXCTL_TNLFBYP 0x4 + +#define FB_DACFXCTL_BEEN 1 +#define FM_DACFXCTL_BEEN 0x2 + +#define FB_DACFXCTL_BNLFBYP 0 +#define FM_DACFXCTL_BNLFBYP 0x1 + +// *** SUBEQFILT *** +#define FB_SUBEQFILT_EQ2EN 7 +#define FM_SUBEQFILT_EQ2EN 0x80 +#define FV_EQ2EN_ENABLE 0x80 +#define FV_EQ2EN_DISABLE 0x0 + +#define FB_SUBEQFILT_EQ2BE 4 +#define FM_SUBEQFILT_EQ2BE 0x70 + +#define FB_SUBEQFILT_EQ1EN 3 +#define FM_SUBEQFILT_EQ1EN 0x8 +#define FV_EQ1EN_ENABLE 0x8 +#define FV_EQ1EN_DISABLE 0x0 + +#define FB_SUBEQFILT_EQ1BE 0 +#define FM_SUBEQFILT_EQ1BE 0x7 + +#define SUBEQFILT_EQEN_ENABLE 0x1 +#define SUBEQFILT_EQEN_DISABLE 0x0 + +// *** SUBCRWDL *** +#define FB_SUBCRWDL_WDATA_L 0 +#define FM_SUBCRWDL_WDATA_L 0xFF + +// *** SUBCRWDM *** +#define FB_SUBCRWDM_WDATA_M 0 +#define FM_SUBCRWDM_WDATA_M 0xFF + +// *** SUBCRWDH *** +#define FB_SUBCRWDH_WDATA_H 0 +#define FM_SUBCRWDH_WDATA_H 0xFF + +// *** SUBCRRDL *** +#define FB_SUBCRRDL_RDATA_L 0 +#define FM_SUBCRRDL_RDATA_L 0xFF + +// *** SUBCRRDM *** +#define FB_SUBCRRDM_RDATA_M 0 +#define FM_SUBCRRDM_RDATA_M 0xFF + +// *** SUBCRRDH *** +#define FB_SUBCRRDH_RDATA_H 0 +#define FM_SUBCRRDH_RDATA_H 0xFF + +// *** SUBCRADD *** +#define FB_SUBCRADD_ADDRESS 0 +#define FM_SUBCRADD_ADDRESS 0xFF + +// *** SUBCRS *** +#define FB_SUBCRS_ACCSTAT 7 +#define FM_SUBCRS_ACCSTAT 0x80 + +// *** SUBMBCEN *** +#define FB_SUBMBCEN_MBCEN3 2 +#define FM_SUBMBCEN_MBCEN3 0x4 +#define FV_MBCEN3_ENABLE 0x4 +#define FV_MBCEN3_DISABLE 0x0 + +#define FB_SUBMBCEN_MBCEN2 1 +#define FM_SUBMBCEN_MBCEN2 0x2 +#define FV_MBCEN2_ENABLE 0x2 +#define FV_MBCEN2_DISABLE 0x0 + +#define FB_SUBMBCEN_MBCEN1 0 +#define FM_SUBMBCEN_MBCEN1 0x1 +#define FV_MBCEN1_ENABLE 0x1 +#define FV_MBCEN1_DISABLE 0x0 + +#define SUBMBCEN_MBCEN_ENABLE 0x1 +#define SUBMBCEN_MBCEN_DISABLE 0x0 + +// *** SUBMBCCTL *** +#define FB_SUBMBCCTL_LVLMODE3 5 +#define FM_SUBMBCCTL_LVLMODE3 0x20 + +#define FB_SUBMBCCTL_WINSEL3 4 +#define FM_SUBMBCCTL_WINSEL3 0x10 + +#define FB_SUBMBCCTL_LVLMODE2 3 +#define FM_SUBMBCCTL_LVLMODE2 0x8 + +#define FB_SUBMBCCTL_WINSEL2 2 +#define FM_SUBMBCCTL_WINSEL2 0x4 + +#define FB_SUBMBCCTL_LVLMODE1 1 +#define FM_SUBMBCCTL_LVLMODE1 0x2 + +#define FB_SUBMBCCTL_WINSEL1 0 +#define FM_SUBMBCCTL_WINSEL1 0x1 + +// *** SUBCLECTL *** +#define FB_SUBCLECTL_LVLMODE 4 +#define FM_SUBCLECTL_LVLMODE 0x10 + +#define FB_SUBCLECTL_WINSEL 3 +#define FM_SUBCLECTL_WINSEL 0x8 + +#define FB_SUBCLECTL_EXPEN 2 +#define FM_SUBCLECTL_EXPEN 0x4 +#define FV_EXPEN_ENABLE 0x4 +#define FV_EXPEN_DISABLE 0x0 + +#define FB_SUBCLECTL_LIMEN 1 +#define FM_SUBCLECTL_LIMEN 0x2 +#define FV_LIMEN_ENABLE 0x2 +#define FV_LIMEN_DISABLE 0x0 + +#define FB_SUBCLECTL_COMPEN 0 +#define FM_SUBCLECTL_COMPEN 0x1 +#define FV_COMPEN_ENABLE 0x1 +#define FV_COMPEN_DISABLE 0x0 + +// *** SUBCLEMUG *** +#define FB_SUBCLEMUG_MUGAIN 0 +#define FM_SUBCLEMUG_MUGAIN 0x1F + +// *** SUBCOMPTHR *** +#define FB_SUBCOMPTHR_THRESH 0 +#define FM_SUBCOMPTHR_THRESH 0xFF + +// *** SUBCOMPRAT *** +#define FB_SUBCOMPRAT_RATIO 0 +#define FM_SUBCOMPRAT_RATIO 0x1F + +// *** SUBCOMPATKL *** +#define FB_SUBCOMPATKL_TCATKL 0 +#define FM_SUBCOMPATKL_TCATKL 0xFF + +// *** SUBCOMPATKH *** +#define FB_SUBCOMPATKH_TCATKH 0 +#define FM_SUBCOMPATKH_TCATKH 0xFF + +// *** SUBCOMPRELL *** +#define FB_SUBCOMPRELL_TCRELL 0 +#define FM_SUBCOMPRELL_TCRELL 0xFF + +// *** SUBCOMPRELH *** +#define FB_SUBCOMPRELH_TCRELH 0 +#define FM_SUBCOMPRELH_TCRELH 0xFF + +// *** SUBLIMTHR *** +#define FB_SUBLIMTHR_THRESH 0 +#define FM_SUBLIMTHR_THRESH 0xFF + +// *** SUBLIMTGT *** +#define FB_SUBLIMTGT_TARGET 0 +#define FM_SUBLIMTGT_TARGET 0xFF + +// *** SUBLIMATKL *** +#define FB_SUBLIMATKL_TCATKL 0 +#define FM_SUBLIMATKL_TCATKL 0xFF + +// *** SUBLIMATKH *** +#define FB_SUBLIMATKH_TCATKH 0 +#define FM_SUBLIMATKH_TCATKH 0xFF + +// *** SUBLIMRELL *** +#define FB_SUBLIMRELL_TCRELL 0 +#define FM_SUBLIMRELL_TCRELL 0xFF + +// *** SUBLIMRELH *** +#define FB_SUBLIMRELH_TCRELH 0 +#define FM_SUBLIMRELH_TCRELH 0xFF + +// *** SUBEXPTHR *** +#define FB_SUBEXPTHR_THRESH 0 +#define FM_SUBEXPTHR_THRESH 0xFF + +// *** SUBEXPRAT *** +#define FB_SUBEXPRAT_RATIO 0 +#define FM_SUBEXPRAT_RATIO 0x7 + +// *** SUBEXPATKL *** +#define FB_SUBEXPATKL_TCATKL 0 +#define FM_SUBEXPATKL_TCATKL 0xFF + +// *** SUBEXPATKH *** +#define FB_SUBEXPATKH_TCATKH 0 +#define FM_SUBEXPATKH_TCATKH 0xFF + +// *** SUBEXPRELL *** +#define FB_SUBEXPRELL_TCRELL 0 +#define FM_SUBEXPRELL_TCRELL 0xFF + +// *** SUBEXPRELH *** +#define FB_SUBEXPRELH_TCRELH 0 +#define FM_SUBEXPRELH_TCRELH 0xFF + +// *** SUBFXCTL *** +#define FB_SUBFXCTL_TEEN 3 +#define FM_SUBFXCTL_TEEN 0x8 + +#define FB_SUBFXCTL_TNLFBYP 2 +#define FM_SUBFXCTL_TNLFBYP 0x4 + +#define FB_SUBFXCTL_BEEN 1 +#define FM_SUBFXCTL_BEEN 0x2 + +#define FB_SUBFXCTL_BNLFBYP 0 +#define FM_SUBFXCTL_BNLFBYP 0x1 + +#endif /* __REDWOODPUBLIC_H__ */ diff --git a/sound/soc/codecs/wm2200.c b/sound/soc/codecs/wm2200.c index d5f4bbf27182..3663b9fd4d65 100644 --- a/sound/soc/codecs/wm2200.c +++ b/sound/soc/codecs/wm2200.c @@ -1155,8 +1155,8 @@ SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_3L, SND_SOC_BYTES_MASK("EQL Coefficients", WM2200_EQL_1, 20, WM2200_EQL_ENA), SND_SOC_BYTES_MASK("EQR Coefficients", WM2200_EQR_1, 20, WM2200_EQR_ENA), -SND_SOC_BYTES("LHPF1 Coefficeints", WM2200_HPLPF1_2, 1), -SND_SOC_BYTES("LHPF2 Coefficeints", WM2200_HPLPF2_2, 1), +SND_SOC_BYTES("LHPF1 Coefficients", WM2200_HPLPF1_2, 1), +SND_SOC_BYTES("LHPF2 Coefficients", WM2200_HPLPF2_2, 1), SOC_SINGLE("OUT1 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_1L, WM2200_OUT1_OSR_SHIFT, 1, 0), diff --git a/sound/soc/codecs/wm5100.c b/sound/soc/codecs/wm5100.c index 87f9a99ce978..ba89d9d711f7 100644 --- a/sound/soc/codecs/wm5100.c +++ b/sound/soc/codecs/wm5100.c @@ -573,10 +573,10 @@ SND_SOC_BYTES_MASK("EQ4 Coefficients", WM5100_EQ4_1, 20, WM5100_EQ4_ENA), SND_SOC_BYTES_MASK("DRC Coefficients", WM5100_DRC1_CTRL1, 5, WM5100_DRCL_ENA | WM5100_DRCR_ENA), -SND_SOC_BYTES("LHPF1 Coefficeints", WM5100_HPLPF1_2, 1), -SND_SOC_BYTES("LHPF2 Coefficeints", WM5100_HPLPF2_2, 1), -SND_SOC_BYTES("LHPF3 Coefficeints", WM5100_HPLPF3_2, 1), -SND_SOC_BYTES("LHPF4 Coefficeints", WM5100_HPLPF4_2, 1), +SND_SOC_BYTES("LHPF1 Coefficients", WM5100_HPLPF1_2, 1), +SND_SOC_BYTES("LHPF2 Coefficients", WM5100_HPLPF2_2, 1), +SND_SOC_BYTES("LHPF3 Coefficients", WM5100_HPLPF3_2, 1), +SND_SOC_BYTES("LHPF4 Coefficients", WM5100_HPLPF4_2, 1), SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L, WM5100_OUT1_OSR_SHIFT, 1, 0), diff --git a/sound/soc/codecs/wm8782.c b/sound/soc/codecs/wm8782.c index 7949703f3d04..317db9a149a7 100644 --- a/sound/soc/codecs/wm8782.c +++ b/sound/soc/codecs/wm8782.c @@ -67,9 +67,18 @@ static int wm8782_probe(struct platform_device *pdev) &soc_component_dev_wm8782, &wm8782_dai, 1); } +#ifdef CONFIG_OF +static const struct of_device_id wm8782_of_match[] = { + { .compatible = "wlf,wm8782", }, + { } +}; +MODULE_DEVICE_TABLE(of, wm8782_of_match); +#endif + static struct platform_driver wm8782_codec_driver = { .driver = { .name = "wm8782", + .of_match_table = of_match_ptr(wm8782_of_match), }, .probe = wm8782_probe, }; diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c index 20fdcae06c6b..f13ef334c0d7 100644 --- a/sound/soc/codecs/wm8904.c +++ b/sound/soc/codecs/wm8904.c @@ -596,7 +596,7 @@ static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), -SOC_ENUM("Left Caputure Mode", lin_mode), +SOC_ENUM("Left Capture Mode", lin_mode), SOC_ENUM("Right Capture Mode", rin_mode), /* No TLV since it depends on mode */ diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c index af062c4f4017..2175dccdf388 100644 --- a/sound/soc/codecs/wm_adsp.c +++ b/sound/soc/codecs/wm_adsp.c @@ -2665,9 +2665,9 @@ int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol, dsp->preloaded = ucontrol->value.integer.value[0]; if (ucontrol->value.integer.value[0]) - snd_soc_dapm_force_enable_pin(dapm, preload); + snd_soc_component_force_enable_pin(component, preload); else - snd_soc_dapm_disable_pin(dapm, preload); + snd_soc_component_disable_pin(component, preload); snd_soc_dapm_sync(dapm); @@ -2851,11 +2851,11 @@ EXPORT_SYMBOL_GPL(wm_adsp2_event); int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component) { - struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); char preload[32]; snprintf(preload, ARRAY_SIZE(preload), "DSP%d Preload", dsp->num); - snd_soc_dapm_disable_pin(dapm, preload); + + snd_soc_component_disable_pin(component, preload); wm_adsp2_init_debugfs(dsp, component); |