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| author |   Misael Lopez Cruz <misael.lopez@ti.com> | 2014-11-12 16:38:05 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2014-11-12 14:55:00 +0000 |
| commit | a7a3324a602cd7ebabfb7f5990006ec4f3d6449f (patch) | |
| tree | f77c68c09dec608db66c5e16b9010bd56359d4f4 /sound/soc/davinci/davinci-mcasp.h | |
| parent | ASoC: davinci-mcasp: Active slots depend on active serializers (diff) | |
| download | linux-dev-a7a3324a602cd7ebabfb7f5990006ec4f3d6449f.tar.xz linux-dev-a7a3324a602cd7ebabfb7f5990006ec4f3d6449f.zip | |
ASoC: davinci-mcasp: Add overrun/underrun event handling
An underrun (playback) event occurs when the serializer transfer
data from the XRBUF buffer to the XRSR shift register, but the
XRBUF hasn't been filled. Similarly, the overrun (capture) event
occurs when data from the XRSR shift register is transferred to
the XRBUF but it hasn't been read yet.
These events are handled as XRUN events that cause the pcm to stop.
The stream has to be explicitly restarted by the userspace which
ensures that after stopping/starting McASP the data transfer is
aligned with DMA. The other possibility was to internally stop and
start McASP without DMA even knowing about it.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/davinci/davinci-mcasp.h')
| -rw-r--r-- | sound/soc/davinci/davinci-mcasp.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.h b/sound/soc/davinci/davinci-mcasp.h index 9737108f0305..79dc511180bf 100644 --- a/sound/soc/davinci/davinci-mcasp.h +++ b/sound/soc/davinci/davinci-mcasp.h @@ -256,6 +256,7 @@ * DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits * DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits */ +#define XRERR BIT(8) /* Transmit/Receive error */ #define XRDATA BIT(5) /* Transmit/Receive data ready */ /* @@ -285,6 +286,16 @@ #define TXDATADMADIS BIT(0) /* + * DAVINCI_MCASP_EVTCTLR_REG - Receiver Interrupt Control Register Bits + */ +#define ROVRN BIT(0) + +/* + * DAVINCI_MCASP_EVTCTLX_REG - Transmitter Interrupt Control Register Bits + */ +#define XUNDRN BIT(0) + +/* * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits */ #define FIFO_ENABLE BIT(16) |