diff options
| author |   Hans de Goede <hdegoede@redhat.com> | 2018-05-11 11:52:16 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2018-05-13 11:30:19 +0900 |
| commit | a3a956a6dddec7ce83bf861c11b479da1057980f (patch) | |
| tree | c707a0a6ca7089ddd5e8a0b93a57a2fbabdafa4e /sound/soc/intel/boards/bytcr_rt5640.c | |
| parent | ASoC: hisilicon: fix spelling mistake: "uknown" -> "unknown" (diff) | |
| download | linux-dev-a3a956a6dddec7ce83bf861c11b479da1057980f.tar.xz linux-dev-a3a956a6dddec7ce83bf861c11b479da1057980f.zip | |
ASoC: Intel: bytcr_rt5640: Fix compile error
Fix the compile error introduced by: "ASoC: Intel: bytcr_rt5640:
Configure PLL1 before using it".
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel/boards/bytcr_rt5640.c')
| -rw-r--r-- | sound/soc/intel/boards/bytcr_rt5640.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/intel/boards/bytcr_rt5640.c b/sound/soc/intel/boards/bytcr_rt5640.c index 404aa7355912..fe46f3b2aecc 100644 --- a/sound/soc/intel/boards/bytcr_rt5640.c +++ b/sound/soc/intel/boards/bytcr_rt5640.c @@ -178,14 +178,14 @@ static int byt_rt5640_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai, } if (ret < 0) { - dev_err(codec_dai->codec->dev, "can't set pll: %d\n", ret); + dev_err(codec_dai->component->dev, "can't set pll: %d\n", ret); return ret; } ret = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_PLL1, rate * 512, SND_SOC_CLOCK_IN); if (ret < 0) { - dev_err(codec_dai->codec->dev, "can't set clock %d\n", ret); + dev_err(codec_dai->component->dev, "can't set clock %d\n", ret); return ret; } |