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| author |   Jayachandran B <jayachandran.b@intel.com> | 2015-12-18 15:12:03 +0530 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2016-01-10 12:19:01 +0000 |
| commit | 0c8ba9d28518822d612de23fc9020b2a66a0228c (patch) | |
| tree | 89295d33fcb50b73dba25302a9979fb013cf9cd0 /sound/soc/intel/skylake/skl.h | |
| parent | Merge branch 'topic/hdac' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-intel (diff) | |
| download | linux-dev-0c8ba9d28518822d612de23fc9020b2a66a0228c.tar.xz linux-dev-0c8ba9d28518822d612de23fc9020b2a66a0228c.zip | |
ASoC: Intel: Skylake: fix reset controller sequencing
MISCBDCGE is a new register for Misc Backbone clock gate control
which is useful to control while resetting the link and ensuring
controller is in required state so add API to control it
HW recommends that we reset with CGCTL.MISCBDCGE disabled, so add
that while doing init chip and reset sequence.
Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel/skylake/skl.h')
| -rw-r--r-- | sound/soc/intel/skylake/skl.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sound/soc/intel/skylake/skl.h b/sound/soc/intel/skylake/skl.h index 36a1b8c5f6d0..8a08bb727991 100644 --- a/sound/soc/intel/skylake/skl.h +++ b/sound/soc/intel/skylake/skl.h @@ -48,6 +48,9 @@ #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 +#define AZX_PCIREG_CGCTL 0x48 +#define AZX_CGCTL_MISCBDCGE_MASK (1 << 6) + struct skl_dsp_resource { u32 max_mcps; u32 max_mem; |