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| author |   Trevor Wu <trevor.wu@mediatek.com> | 2022-09-27 23:11:41 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2022-09-28 12:30:48 +0100 |
| commit | 7ba6546b547c75b0196029c7e0aaaab2eb6694a4 (patch) | |
| tree | 7c89164e80198d54d456c21841eef63434f80d14 /sound/soc | |
| parent | Fix PM disable depth imbalance in stm32 probe (diff) | |
| download | linux-dev-7ba6546b547c75b0196029c7e0aaaab2eb6694a4.tar.xz linux-dev-7ba6546b547c75b0196029c7e0aaaab2eb6694a4.zip | |
ASoC: mediatek: mt8195: update audio tuner settings
Audio tuner is used to handle clock drift between 26M and APLL domain.
It's expected when abs(chg_cnt) equals to upper bound, tuner updates pcw
setting automatically, and then abs(chg_cnt) decreases.
In the stress test, we found abs(chg_cnt) possibly equals to 2 at the
unexpected timing. This results in wrong pcw updating.
Finally, abs(chg_cnt) will always be larger than upper bound,
As a result, we update the upper bound to 3 to handle the corner case.
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220927151141.11846-1-trevor.wu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc')
| -rw-r--r-- | sound/soc/mediatek/mt8195/mt8195-afe-clk.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c index 2ee3872c83c3..9ca2cb8c8a9c 100644 --- a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c +++ b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c @@ -117,7 +117,7 @@ static struct mt8195_afe_tuner_cfg mt8195_afe_tuner_cfgs[MT8195_AUD_PLL_NUM] = { .upper_bound_reg = AFE_APLL_TUNER_CFG, .upper_bound_shift = 8, .upper_bound_maskbit = 0xff, - .upper_bound_default = 0x2, + .upper_bound_default = 0x3, }, [MT8195_AUD_PLL2] = { .id = MT8195_AUD_PLL2, @@ -135,7 +135,7 @@ static struct mt8195_afe_tuner_cfg mt8195_afe_tuner_cfgs[MT8195_AUD_PLL_NUM] = { .upper_bound_reg = AFE_APLL_TUNER_CFG1, .upper_bound_shift = 8, .upper_bound_maskbit = 0xff, - .upper_bound_default = 0x2, + .upper_bound_default = 0x3, }, [MT8195_AUD_PLL3] = { .id = MT8195_AUD_PLL3, |