diff options
author | William Cohen <wcohen@redhat.com> | 2021-09-26 20:51:15 -0400 |
---|---|---|
committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2021-09-27 09:33:44 -0300 |
commit | 0ba37e05c240c7b38e5a327a96f404798a8698ff (patch) | |
tree | 311b5d4a3e8c159297eaa96502d62760e9a9daac /tools/perf/arch | |
parent | perf list: Display pmu prefix for partially supported hybrid cache events (diff) | |
download | linux-dev-0ba37e05c240c7b38e5a327a96f404798a8698ff.tar.xz linux-dev-0ba37e05c240c7b38e5a327a96f404798a8698ff.zip |
perf annotate: Add riscv64 support
This patch adds basic arch initialization and instruction associate
support for the riscv64 CPU architecture.
Example output:
$ perf annotate --stdio2
Samples: 122K of event 'task-clock:u', 4000 Hz, Event count (approx.): 30637250000, [percent: local period]
strcmp() /usr/lib64/libc-2.32.so
Percent
Disassembly of section .text:
0000000000069a30 <strcmp>:
__GI_strcmp():
const unsigned char *s2 = (const unsigned char *) p2;
unsigned char c1, c2;
do
{
c1 = (unsigned char) *s1++;
37.30 lbu a5,0(a0)
c2 = (unsigned char) *s2++;
1.23 addi a1,a1,1
c1 = (unsigned char) *s1++;
18.68 addi a0,a0,1
c2 = (unsigned char) *s2++;
1.37 lbu a4,-1(a1)
if (c1 == '\0')
18.71 ↓ beqz a5,18
return c1 - c2;
}
Signed-off-by: William Cohen <wcohen@redhat.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-riscv@lists.infradead.org
Link: http://lore.kernel.org/lkml/20210927005115.610264-1-wcohen@redhat.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/arch')
-rw-r--r-- | tools/perf/arch/riscv64/annotate/instructions.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/tools/perf/arch/riscv64/annotate/instructions.c b/tools/perf/arch/riscv64/annotate/instructions.c new file mode 100644 index 000000000000..869a0eb28953 --- /dev/null +++ b/tools/perf/arch/riscv64/annotate/instructions.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 + +static +struct ins_ops *riscv64__associate_ins_ops(struct arch *arch, const char *name) +{ + struct ins_ops *ops = NULL; + + if (!strncmp(name, "jal", 3) || + !strncmp(name, "jr", 2) || + !strncmp(name, "call", 4)) + ops = &call_ops; + else if (!strncmp(name, "ret", 3)) + ops = &ret_ops; + else if (name[0] == 'j' || name[0] == 'b') + ops = &jump_ops; + else + return NULL; + + arch__associate_ins_ops(arch, name, ops); + + return ops; +} + +static +int riscv64__annotate_init(struct arch *arch, char *cpuid __maybe_unused) +{ + if (!arch->initialized) { + arch->associate_instruction_ops = riscv64__associate_ins_ops; + arch->initialized = true; + arch->objdump.comment_char = '#'; + } + + return 0; +} |