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| author |   Adrian Hunter <adrian.hunter@intel.com> | 2017-05-26 11:17:37 +0300 |
|---|---|---|
| committer |   Arnaldo Carvalho de Melo <acme@redhat.com> | 2017-06-30 11:50:55 -0300 |
| commit | 38b65b0891dc129dc0a5ce148a21c481e667b395 (patch) | |
| tree | f2d180d2fbf0f10a84d38b1bbeaa7413de7a0a3a /tools/perf/builtin-script.c | |
| parent | perf intel-pt: Update documentation to include new ptwrite and power events (diff) | |
| download | linux-dev-38b65b0891dc129dc0a5ce148a21c481e667b395.tar.xz linux-dev-38b65b0891dc129dc0a5ce148a21c481e667b395.zip | |
perf intel-pt: Do not use TSC packets for calculating CPU cycles to TSC
CBR (core-to-bus ratio) packets provide an indication of CPU frequency. A
more accurate measure can be made by counting the cycles (given by CYC
packets) in between other timing packets (either MTC or TSC). Using TSC
packets has at least 2 issues: 1) timing might have stopped (e.g. mwait) or
2) TSC packets within PSB+ might slip past CYC packets. For now, simply do
not use TSC packets for calculating CPU cycles to TSC. That leaves the case
where 2 MTC packets are used, otherwise falling back to the CBR value.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Link: http://lkml.kernel.org/r/1495786658-18063-37-git-send-email-adrian.hunter@intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/builtin-script.c')
0 files changed, 0 insertions, 0 deletions