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author | 2022-09-07 16:49:30 +0100 | |
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committer | 2022-10-04 08:55:21 -0300 | |
commit | 3657ad4b0fb6a6c3df12cec92013614212f5f401 (patch) | |
tree | 55454dc9ec724abf169be23179be05cdf61e493b /tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/bus.json | |
parent | perf timechart: Add p_state_end helper (diff) | |
download | linux-dev-3657ad4b0fb6a6c3df12cec92013614212f5f401.tar.xz linux-dev-3657ad4b0fb6a6c3df12cec92013614212f5f401.zip |
perf vendor events: Update events for Neoverse E1
These CPUs contain the same PMU events (as per the Arm Technical
Reference manuals for Cortex A65 and Neoverse E1)
This de-duplicates event data, and avoids issues in previous E1 event
data (not present in A65 data)
* Missing implementation defined events
* Inclusion of events that are not implemented:
- L1D_CACHE_ALLOCATE
- SAMPLE_POP
- SAMPLE_FEED
- SAMPLE_FILTRATE
- SAMPLE_COLLISION
Reviewed-by: John Garry <john.garry@huawei.com>
Signed-off-by: Nick Forrington <nick.forrington@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20220907154932.60808-1-nick.forrington@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/bus.json')
-rw-r--r-- | tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/bus.json | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] |