perf vendor events arm64: Fix commas so PMU event files are valid JSON

No functional change.

Add and remove extra commas in the arm64 JSON files so that the files
can be parsed and validated by other utilities such as Python that fail
to parse invalid JSON.

Committer testing:

Before:

  $ diffstat -l -p1 /wb/1.patch | while read filename ; do echo $filename ; cat $filename | json_verify ; done
  tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json
  parse error: invalid object key (must be a string)
                                          [     {         "ArchStdEvent"
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json
  parse error: invalid object key (must be a string)
                                          [     {         "ArchStdEvent"
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
  parse error: invalid object key (must be a string)
                                          [     {         "ArchStdEvent"
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json
  parse error: unallowed token at this point in JSON text
                                          [     {         "PublicDescrip
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json
  parse error: invalid object key (must be a string)
                                          [     {         "ArchStdEvent"
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json
  parse error: invalid object key (must be a string)
                                          [     {         "ArchStdEvent"
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json
  parse error: invalid object key (must be a string)
                                          [     {         "ArchStdEvent"
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json
  parse error: invalid object key (must be a string)
                                          [     {         "ArchStdEvent"
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json
  parse error: unallowed token at this point in JSON text
                                          [     {         "PublicDescrip
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
  parse error: invalid object key (must be a string)
                                          [   {     "ArchStdEvent":  "BR
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
  parse error: invalid object key (must be a string)
                                          [   {         "ArchStdEvent":
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
  parse error: invalid object key (must be a string)
                                          [   {         "ArchStdEvent":
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
  parse error: invalid object key (must be a string)
                                          [     {         "ArchStdEvent"
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/armv8-recommended.json
  parse error: after array element, I expect ',' or ']'
                                          [     {         "PublicDescrip
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
  parse error: invalid object key (must be a string)
                                          [     {         "ArchStdEvent"
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
  parse error: invalid object key (must be a string)
                                          [     {         "ArchStdEvent"
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
  parse error: invalid object key (must be a string)
                                          [    { 	    "EventCode": "0x00
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json
  parse error: invalid object key (must be a string)
                                          [    { 	    "EventCode": "0x00
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
  parse error: invalid object key (must be a string)
                                          [    { 	    "EventCode": "0x00
                       (right here) ------^
  JSON is invalid
  $

After:

  $ diffstat -l -p1 /wb/1.patch | while read filename ; do echo $filename ; cat $filename | json_verify ; done
  tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/armv8-recommended.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json
  JSON is valid
  tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
  JSON is valid
  $

Signed-off-by: James Clark <james.clark@arm.com>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: John Garry <john.garry@huawei.com>
Cc: Kevin Mooney <kevin.mooney@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: nd@arm.com
Link: http://lore.kernel.org/lkml/20191112160342.26470-1-james.clark@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

4 files changed, 65 insertions, 65 deletions

diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
index 0b0e6b26605b..8f5cf88aaf38 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
@@ -1,6 +1,6 @@
 [
   {
-    "ArchStdEvent":  "BR_INDIRECT_SPEC",
+    "ArchStdEvent":  "BR_INDIRECT_SPEC"
   },
   {
     "EventCode": "0xC9",
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
index ce33b2553277..0a70b82f753f 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
@@ -1,8 +1,8 @@
 [
   {
-        "ArchStdEvent": "BUS_ACCESS_RD",
+        "ArchStdEvent": "BUS_ACCESS_RD"
   },
   {
-        "ArchStdEvent": "BUS_ACCESS_WR",
+        "ArchStdEvent": "BUS_ACCESS_WR"
   }
 ]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
index 6cc6cbd7bf0b..e9f7e4c3900d 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
@@ -1,9 +1,9 @@
 [
   {
-        "ArchStdEvent": "EXC_IRQ",
+        "ArchStdEvent": "EXC_IRQ"
   },
   {
-        "ArchStdEvent": "EXC_FIQ",
+        "ArchStdEvent": "EXC_FIQ"
   },
   {
         "EventCode": "0xC6",
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
index 0ac9b7927450..543c7692677a 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
@@ -1,179 +1,179 @@
 [
     {
-        "ArchStdEvent": "L1D_CACHE_RD",
+        "ArchStdEvent": "L1D_CACHE_RD"
     },
     {
-        "ArchStdEvent": "L1D_CACHE_WR",
+        "ArchStdEvent": "L1D_CACHE_WR"
     },
     {
-        "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
     },
     {
-        "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
     },
     {
-        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
     },
     {
-        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
     },
     {
-        "ArchStdEvent": "L1D_CACHE_INVAL",
+        "ArchStdEvent": "L1D_CACHE_INVAL"
     },
     {
-        "ArchStdEvent": "L1D_TLB_REFILL_RD",
+        "ArchStdEvent": "L1D_TLB_REFILL_RD"
     },
     {
-        "ArchStdEvent": "L1D_TLB_REFILL_WR",
+        "ArchStdEvent": "L1D_TLB_REFILL_WR"
     },
     {
-        "ArchStdEvent": "L2D_CACHE_RD",
+        "ArchStdEvent": "L2D_CACHE_RD"
     },
     {
-        "ArchStdEvent": "L2D_CACHE_WR",
+        "ArchStdEvent": "L2D_CACHE_WR"
     },
     {
-        "ArchStdEvent": "L2D_CACHE_REFILL_RD",
+        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
     },
     {
-        "ArchStdEvent": "L2D_CACHE_REFILL_WR",
+        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
     },
     {
-        "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
+        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
     },
     {
-        "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
     },
     {
-        "ArchStdEvent": "L2D_CACHE_INVAL",
+        "ArchStdEvent": "L2D_CACHE_INVAL"
     },
     {
-        "ArchStdEvent": "BUS_ACCESS_RD",
+        "ArchStdEvent": "BUS_ACCESS_RD"
     },
     {
-        "ArchStdEvent": "BUS_ACCESS_WR",
+        "ArchStdEvent": "BUS_ACCESS_WR"
     },
     {
-        "ArchStdEvent": "BUS_ACCESS_SHARED",
+        "ArchStdEvent": "BUS_ACCESS_SHARED"
     },
     {
-        "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
+        "ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
     },
     {
-        "ArchStdEvent": "BUS_ACCESS_NORMAL",
+        "ArchStdEvent": "BUS_ACCESS_NORMAL"
     },
     {
-        "ArchStdEvent": "BUS_ACCESS_PERIPH",
+        "ArchStdEvent": "BUS_ACCESS_PERIPH"
     },
     {
-        "ArchStdEvent": "MEM_ACCESS_RD",
+        "ArchStdEvent": "MEM_ACCESS_RD"
     },
     {
-        "ArchStdEvent": "MEM_ACCESS_WR",
+        "ArchStdEvent": "MEM_ACCESS_WR"
     },
     {
-        "ArchStdEvent": "UNALIGNED_LD_SPEC",
+        "ArchStdEvent": "UNALIGNED_LD_SPEC"
     },
     {
-        "ArchStdEvent": "UNALIGNED_ST_SPEC",
+        "ArchStdEvent": "UNALIGNED_ST_SPEC"
     },
     {
-        "ArchStdEvent": "UNALIGNED_LDST_SPEC",
+        "ArchStdEvent": "UNALIGNED_LDST_SPEC"
     },
     {
-        "ArchStdEvent": "LDREX_SPEC",
+        "ArchStdEvent": "LDREX_SPEC"
     },
     {
-        "ArchStdEvent": "STREX_PASS_SPEC",
+        "ArchStdEvent": "STREX_PASS_SPEC"
     },
     {
-        "ArchStdEvent": "STREX_FAIL_SPEC",
+        "ArchStdEvent": "STREX_FAIL_SPEC"
     },
     {
-        "ArchStdEvent": "LD_SPEC",
+        "ArchStdEvent": "LD_SPEC"
     },
     {
-        "ArchStdEvent": "ST_SPEC",
+        "ArchStdEvent": "ST_SPEC"
     },
     {
-        "ArchStdEvent": "LDST_SPEC",
+        "ArchStdEvent": "LDST_SPEC"
     },
     {
-        "ArchStdEvent": "DP_SPEC",
+        "ArchStdEvent": "DP_SPEC"
     },
     {
-        "ArchStdEvent": "ASE_SPEC",
+        "ArchStdEvent": "ASE_SPEC"
     },
     {
-        "ArchStdEvent": "VFP_SPEC",
+        "ArchStdEvent": "VFP_SPEC"
     },
     {
-        "ArchStdEvent": "PC_WRITE_SPEC",
+        "ArchStdEvent": "PC_WRITE_SPEC"
     },
     {
-        "ArchStdEvent": "CRYPTO_SPEC",
+        "ArchStdEvent": "CRYPTO_SPEC"
     },
     {
-        "ArchStdEvent": "BR_IMMED_SPEC",
+        "ArchStdEvent": "BR_IMMED_SPEC"
     },
     {
-        "ArchStdEvent": "BR_RETURN_SPEC",
+        "ArchStdEvent": "BR_RETURN_SPEC"
     },
     {
-        "ArchStdEvent": "BR_INDIRECT_SPEC",
+        "ArchStdEvent": "BR_INDIRECT_SPEC"
     },
     {
-        "ArchStdEvent": "ISB_SPEC",
+        "ArchStdEvent": "ISB_SPEC"
     },
     {
-        "ArchStdEvent": "DSB_SPEC",
+        "ArchStdEvent": "DSB_SPEC"
     },
     {
-        "ArchStdEvent": "DMB_SPEC",
+        "ArchStdEvent": "DMB_SPEC"
     },
     {
-        "ArchStdEvent": "EXC_UNDEF",
+        "ArchStdEvent": "EXC_UNDEF"
     },
     {
-        "ArchStdEvent": "EXC_SVC",
+        "ArchStdEvent": "EXC_SVC"
     },
     {
-        "ArchStdEvent": "EXC_PABORT",
+        "ArchStdEvent": "EXC_PABORT"
     },
     {
-        "ArchStdEvent": "EXC_DABORT",
+        "ArchStdEvent": "EXC_DABORT"
     },
     {
-        "ArchStdEvent": "EXC_IRQ",
+        "ArchStdEvent": "EXC_IRQ"
     },
     {
-        "ArchStdEvent": "EXC_FIQ",
+        "ArchStdEvent": "EXC_FIQ"
     },
     {
-        "ArchStdEvent": "EXC_SMC",
+        "ArchStdEvent": "EXC_SMC"
     },
     {
-        "ArchStdEvent": "EXC_HVC",
+        "ArchStdEvent": "EXC_HVC"
     },
     {
-        "ArchStdEvent": "EXC_TRAP_PABORT",
+        "ArchStdEvent": "EXC_TRAP_PABORT"
     },
     {
-        "ArchStdEvent": "EXC_TRAP_DABORT",
+        "ArchStdEvent": "EXC_TRAP_DABORT"
     },
     {
-        "ArchStdEvent": "EXC_TRAP_OTHER",
+        "ArchStdEvent": "EXC_TRAP_OTHER"
     },
     {
-        "ArchStdEvent": "EXC_TRAP_IRQ",
+        "ArchStdEvent": "EXC_TRAP_IRQ"
     },
     {
-        "ArchStdEvent": "EXC_TRAP_FIQ",
+        "ArchStdEvent": "EXC_TRAP_FIQ"
     },
     {
-        "ArchStdEvent": "RC_LD_SPEC",
+        "ArchStdEvent": "RC_LD_SPEC"
     },
     {
-        "ArchStdEvent": "RC_ST_SPEC",
-    },
+        "ArchStdEvent": "RC_ST_SPEC"
+    }
 ]