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authorSukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>2017-07-11 17:16:00 -0400
committerArnaldo Carvalho de Melo <acme@redhat.com>2017-07-18 23:14:06 -0300
commit826db0f154ba5bee7d913635644a6f61f993a9b3 (patch)
tree7cd51d5018ad9ec8a905d77cf4707a11a2a6fa63 /tools/perf/pmu-events/arch/powerpc/power9/floating-point.json
parentperf pmu-events: Support additional POWER8+ PVR in mapfile (diff)
downloadlinux-dev-826db0f154ba5bee7d913635644a6f61f993a9b3.tar.xz
linux-dev-826db0f154ba5bee7d913635644a6f61f993a9b3.zip
perf vendor events: Add POWER9 PMU events
Add POWER9 PMU events. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Cc: Andi Kleen <andi@firstfloor.org> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Link: http://lkml.kernel.org/n/tip-i08irl1x1i914xsikiomvqip@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/powerpc/power9/floating-point.json')
-rw-r--r--tools/perf/pmu-events/arch/powerpc/power9/floating-point.json44
1 files changed, 44 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/floating-point.json b/tools/perf/pmu-events/arch/powerpc/power9/floating-point.json
new file mode 100644
index 000000000000..d4e4669c1cf3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power9/floating-point.json
@@ -0,0 +1,44 @@
+[
+ {,
+ "EventCode": "0x10058",
+ "EventName": "PM_MEM_LOC_THRESH_IFU",
+ "BriefDescription": "Local Memory above threshold for IFU speculation control",
+ "PublicDescription": ""
+ },
+ {,
+ "EventCode": "0x4505E",
+ "EventName": "PM_FLOP_CMPL",
+ "BriefDescription": "Floating Point Operation Finished",
+ "PublicDescription": ""
+ },
+ {,
+ "EventCode": "0x1415A",
+ "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
+ "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
+ "PublicDescription": ""
+ },
+ {,
+ "EventCode": "0x2D028",
+ "EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
+ "BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache",
+ "PublicDescription": ""
+ },
+ {,
+ "EventCode": "0x2D154",
+ "EventName": "PM_MRK_DERAT_MISS_64K",
+ "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K",
+ "PublicDescription": ""
+ },
+ {,
+ "EventCode": "0x30012",
+ "EventName": "PM_FLUSH_COMPLETION",
+ "BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush",
+ "PublicDescription": ""
+ },
+ {,
+ "EventCode": "0x4016E",
+ "EventName": "PM_THRESH_NOT_MET",
+ "BriefDescription": "Threshold counter did not meet threshold",
+ "PublicDescription": ""
+ }
+]