diff options
author | Zhengjun Xing <zhengjun.xing@linux.intel.com> | 2022-06-07 17:27:48 +0800 |
---|---|---|
committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2022-07-26 16:31:54 -0300 |
commit | 5fa2481cdfe05855ba99a2a9028fd2c9c1af2dcf (patch) | |
tree | d2d2ecf31ba10579866021ed2f0d602389a28953 /tools/perf/pmu-events/arch/x86/alderlake/other.json | |
parent | perf inject: Fix spelling mistake "theads" -> "threads" (diff) | |
download | linux-dev-5fa2481cdfe05855ba99a2a9028fd2c9c1af2dcf.tar.xz linux-dev-5fa2481cdfe05855ba99a2a9028fd2c9c1af2dcf.zip |
perf vendor events intel: Update event list for Alderlake
Update JSON event list for Alderlake to perf.
It is a hybrid event list for both Atom and Core.
Based on JSON list v1.11:
https://download.01.org/perfmon/ADL/
Signed-off-by: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220607092749.1976878-1-zhengjun.xing@linux.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/alderlake/other.json')
-rw-r--r-- | tools/perf/pmu-events/arch/x86/alderlake/other.json | 43 |
1 files changed, 19 insertions, 24 deletions
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/other.json b/tools/perf/pmu-events/arch/x86/alderlake/other.json index dc810f093fb0..b575275654a2 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/other.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/other.json @@ -1,7 +1,7 @@ [ { "BriefDescription": "Counts demand data reads that have any type of response.", - "Counter": "0,1,2,3", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -12,7 +12,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", - "Counter": "0,1,2,3", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -23,7 +23,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of response.", - "Counter": "0,1,2,3", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -33,74 +33,68 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc1", - "EventName": "ASSISTS.ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x1f", - "Unit": "cpu_core" - }, - { - "BriefDescription": "Count all other microcode assist beyond FP, AVX_TILE_MIX and A/D assists (counted by their own sub-events). This includes assists at uop writeback like AVX* load/store (non-FP) assists, Null Assist in SNC (due to lack of FP precision format convert with FMA3x3 uarch) or assists generated by ROB (like assists to due to Missprediction for FSW register - fixed in SNC)", + "BriefDescription": "ASSISTS.HARDWARE", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.HARDWARE", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x4", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "ASSISTS.PAGE_FAULT", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.PAGE_FAULT", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x8", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "CORE_POWER.LICENSE_1", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LICENSE_1", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "CORE_POWER.LICENSE_2", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LICENSE_2", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", + "Speculative": "1", "UMask": "0x4", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "CORE_POWER.LICENSE_3", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LICENSE_3", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", + "Speculative": "1", "UMask": "0x8", "Unit": "cpu_core" }, { "BriefDescription": "Counts demand data reads that have any type of response.", - "Counter": "0,1,2,3", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -111,7 +105,7 @@ }, { "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", - "Counter": "0,1,2,3", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -122,7 +116,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of response.", - "Counter": "0,1,2,3", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2A,0x2B", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -132,7 +126,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "XQ.FULL_CYCLES", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "CounterMask": "1", @@ -140,7 +134,8 @@ "EventName": "XQ.FULL_CYCLES", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" } -]
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