diff options
| author |   Ian Rogers <irogers@google.com> | 2022-07-27 15:08:10 -0700 |
|---|---|---|
| committer |   Arnaldo Carvalho de Melo <acme@redhat.com> | 2022-07-28 16:07:20 -0300 |
| commit | beb2db9bed367ea28433f4a1088f0be2069529e5 (patch) | |
| tree | 75534d785a55839ccd73d9e61431f98f81f84fa1 /tools/perf/pmu-events/arch/x86 | |
| parent | perf vendor events: Update Intel elkhartlake (diff) | |
| download | linux-dev-beb2db9bed367ea28433f4a1088f0be2069529e5.tar.xz linux-dev-beb2db9bed367ea28433f4a1088f0be2069529e5.zip | |
perf vendor events: Update goldmont mapfile.csv
Align end of file whitespace with what is generated by:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py
Modify mapfile.csv to have a missing goldmont cpuid.
Event json remains at v13, there are no goldmont metrics.
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20220727220832.2865794-9-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86')
7 files changed, 7 insertions, 7 deletions
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/cache.json b/tools/perf/pmu-events/arch/x86/goldmont/cache.json index 0b887d73b7f3..ed957d4f9c6d 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/cache.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/cache.json @@ -1300,4 +1300,4 @@ "SampleAfterValue": "100007", "UMask": "0x1" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json index bb364a04a75f..37174392a510 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json @@ -30,4 +30,4 @@ "SampleAfterValue": "2000003", "UMask": "0x8" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json index 120ff65897c0..216da6e121c8 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json @@ -79,4 +79,4 @@ "SampleAfterValue": "200003", "UMask": "0x1" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmont/memory.json b/tools/perf/pmu-events/arch/x86/goldmont/memory.json index 6252503f68a1..9f6f0328249e 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/memory.json @@ -31,4 +31,4 @@ "SampleAfterValue": "200003", "UMask": "0x4" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json index 5dba4313013f..42ff0b134aeb 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json @@ -354,7 +354,7 @@ "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", - "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors.", + "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors.", "SampleAfterValue": "200003", "UMask": "0x1" }, diff --git a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json index d5e89c74a9be..2e17e02e1463 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json @@ -75,4 +75,4 @@ "SampleAfterValue": "200003", "UMask": "0x2" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 195c61157da7..17047a972c16 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -6,7 +6,7 @@ GenuineIntel-6-56,v23,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core GenuineIntel-6-96,v1.03,elkhartlake,core -GenuineIntel-6-5C,v8,goldmont,core +GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1,goldmontplus,core GenuineIntel-6-3C,v24,haswell,core GenuineIntel-6-45,v24,haswell,core |