diff options
| author |   John Garry <john.garry@huawei.com> | 2020-10-22 19:02:27 +0800 |
|---|---|---|
| committer |   Arnaldo Carvalho de Melo <acme@redhat.com> | 2020-11-04 09:42:41 -0300 |
| commit | 644bf4b0f7acde641d3db200b4db66977e96c3bd (patch) | |
| tree | 62c1d04ca3469a8c7989bb374d7e4eb3cd6747eb /tools/perf/pmu-events/arch | |
| parent | perf jevents: Tidy error handling (diff) | |
| download | linux-dev-644bf4b0f7acde641d3db200b4db66977e96c3bd.tar.xz linux-dev-644bf4b0f7acde641d3db200b4db66977e96c3bd.zip | |
perf jevents: Add test for arch std events
Recently there was an undetected breakage for std arch event support.
Add support in "PMU events" testcase to detect such breakages.
For this, the "test" arch needs has support added to process std arch
events. And a test event is added for the test, ifself.
Also add a few code comments to help understand the code a bit better.
Committer testing:
Before:
# perf test -vv pmu |& grep l3_cache_rd
#
After:
# perf test -vv pmu |& grep l3_cache_rd
testing event table l3_cache_rd: pass
testing aliases PMU cpu: matched event l3_cache_rd
#
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-By: Kajol Jain<kjain@linux.ibm.com>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Link: https://lore.kernel.org/r/1603364547-197086-3-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch')
| -rw-r--r-- | tools/perf/pmu-events/arch/test/arch-std-events.json | 8 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/test/test_cpu/cache.json | 5 |
2 files changed, 13 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/test/arch-std-events.json b/tools/perf/pmu-events/arch/test/arch-std-events.json new file mode 100644 index 000000000000..43f6f729d6ae --- /dev/null +++ b/tools/perf/pmu-events/arch/test/arch-std-events.json @@ -0,0 +1,8 @@ +[ + { + "PublicDescription": "Attributable Level 3 cache access, read", + "EventCode": "0x40", + "EventName": "L3_CACHE_RD", + "BriefDescription": "L3 cache access, read" + } +] diff --git a/tools/perf/pmu-events/arch/test/test_cpu/cache.json b/tools/perf/pmu-events/arch/test/test_cpu/cache.json new file mode 100644 index 000000000000..036d0efdb2bb --- /dev/null +++ b/tools/perf/pmu-events/arch/test/test_cpu/cache.json @@ -0,0 +1,5 @@ +[ + { + "ArchStdEvent": "L3_CACHE_RD" + } +]
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