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| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2020-03-16 11:38:43 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2020-03-16 20:28:26 +0000 |
| commit | f899f786d181e03f6ca29319bd90ba62231cb44b (patch) | |
| tree | b2c4ca26b16b1df349ce393c2ab24d82ef36ec36 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | drm/i915/gt: Restrict gen7 w/a batch to Haswell (diff) | |
drm/i915: Move GGTT fence registers under gt/
Since the fence registers control HW detiling through the GGTT
aperture, make them a part of the intel_ggtt under gt/
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200316113846.4974-1-chris@chris-wilson.co.uk
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions