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| author | 2021-01-22 21:51:39 -0600 | |
|---|---|---|
| committer | 2021-03-23 22:59:02 -0400 | |
| commit | 79194dacb26a1b31c6d3259144c371795612ce75 (patch) | |
| tree | 5da30251cd6c5aaf9eabf05f58d284f8b140dcd4 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | drm/amdgpu: update mmhub client ids for Aldebaran (diff) | |
drm/amdgpu: Fix GART page table s-bit
For the new 2-level GART table, the last PDE0 points
to PTB. Since PTB is in vram and right now we are
runing under s=0 mode (vram is treated as FB carveout),
so the s bit of this PDE0 should be set to 0.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions
