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| author |   Eryk Brol <eryk.brol@amd.com> | 2020-06-19 14:42:09 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-08-17 14:08:34 -0400 |
| commit | bcc6aa61c82d4f12df3ecc884a9eef9d566edae9 (patch) | |
| tree | 7b5df12ff642e55f89fe0a7dbb2cfc98e255eb77 /tools/perf/scripts/python/bin | |
| parent | drm/amd/display: fix dcn3 wide timing dsc validation (diff) | |
drm/amd/display: Fix DSC force enable on SST
[why]
Previously when force enabling DSC on SST display we unknowingly
supressed lane count, which caused DSC to be enabled automatically.
[how]
By adding an additional flag to force enable DSC in dc_dsc.c DSC can
always be enabled with debugfs dsc_clock_en forced to 1
Cc: stable@vger.kernel.org
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions