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| author |   Chen-Yu Tsai <wens@csie.org> | 2017-05-22 14:25:48 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-06-07 15:32:16 +0200 |
| commit | f2fe1b640f8d5c3567ea1088544bf55e4d9654d8 (patch) | |
| tree | 5fd250bdd847ce47cf21e0bbf41d6562af57c4c7 /tools/perf/scripts/python/bin | |
| parent | clk: sunxi-ng: a83t: Fix PLL lock status register offset (diff) | |
clk: sunxi-ng: a83t: Fix audio PLL divider offset
The divider of the audio PLL has an offset of 1.
Fix this in the driver.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions