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| author |   Stephen Boyd <sboyd@codeaurora.org> | 2016-07-01 17:27:14 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-07-01 17:27:14 -0700 |
| commit | 345c42964c28ed6cf6832d823972b74cc94ebae3 (patch) | |
| tree | 3394964c5fe323aba4a676f62bb1921107a7877b /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | clk: fixed-factor: Allow for a few clocks to change the parent rate (diff) | |
| parent | clk: tegra: Initialize UTMI PLL when enabling PLLU (diff) | |
| download | linux-dev-345c42964c28ed6cf6832d823972b74cc94ebae3.tar.xz linux-dev-345c42964c28ed6cf6832d823972b74cc94ebae3.zip | |
Merge tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
Pull tegra clk driver updates from Thierry Reding:
Fixes and enhancements mostly for Tegra210 clocks that allow DSI and
HDMI to work on Tegra X1. There's also a refactoring, including fixes,
the USB PLL.
* tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: Initialize UTMI PLL when enabling PLLU
clk: tegra: Micro-optimize Tegra210 clock setup
clk: tegra: Make sor_safe the parent of dpaux and dpaux1
clk: tegra: Mark timer clock as critical
clk: tegra: Enable sor1 and sor1_src on Tegra210
clk: tegra: Squash sor1 safe/brick/src into a single mux
clk: tegra: Disable spread spectrum on pll_d2
clk: tegra: Fixup post dividers on Tegra210
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions