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| author |   Peter Ujfalusi <peter.ujfalusi@ti.com> | 2016-02-25 16:50:18 +0200 |
|---|---|---|
| committer |   Paul Walmsley <paul@pwsan.com> | 2016-03-01 01:55:59 -0700 |
| commit | 34b4182ce5fd284bff38764f8e73e2160b49d8e9 (patch) | |
| tree | 9e291e2a5bbfae21a9287b00ac446ec08becd2b6 /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | ARM: DRA7: hwmod: Add custom reset handler for PCIeSS (diff) | |
| download | linux-dev-34b4182ce5fd284bff38764f8e73e2160b49d8e9.tar.xz linux-dev-34b4182ce5fd284bff38764f8e73e2160b49d8e9.zip | |
ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1
Add hwmod data for the eDMA blocks:
- TPCC: Third-party channel controller
- TPTC0: Third-party transfer controller 0
- TPTC1: Third-party transfer controller 1
The TPCC's clock gating status follows the status of its clock and
power domain. This means that the hwmod code can not directly control
the TPCC enable/disable status.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[paul@pwsan.com: rephrased last two sentences of the patch description]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions