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| author |   Stephen Boyd <sboyd@codeaurora.org> | 2016-08-29 17:08:35 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-08-29 17:08:35 -0700 |
| commit | dc7066c54107255f5f9a11bf3f82417c9b1aef51 (patch) | |
| tree | 63709e66975a85f78aac16410a5f23d8c3828e9b /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2 (diff) | |
| parent | clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399 (diff) | |
| download | linux-dev-dc7066c54107255f5f9a11bf3f82417c9b1aef51.tar.xz linux-dev-dc7066c54107255f5f9a11bf3f82417c9b1aef51.zip | |
Merge tag 'v4.8-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes
Some fixes for rk3399 register errors that revealed themself
during actual use.
* tag 'v4.8-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399
clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399
clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399
clk: rockchip: fix rk3399 aclk_vio gate bit
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions