diff options
| author |   Dong Aisheng <aisheng.dong@nxp.com> | 2016-06-08 22:33:36 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2016-06-12 21:21:41 +0800 |
| commit | f83d31635cd65dd10eddaac1809b9e400d385d43 (patch) | |
| tree | 16114810176382e8255a504e5f41d58e905fbc44 /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | clk: imx7d: correct dram pll type (diff) | |
| download | linux-dev-f83d31635cd65dd10eddaac1809b9e400d385d43.tar.xz linux-dev-f83d31635cd65dd10eddaac1809b9e400d385d43.zip | |
clk: imx: fix pll clock parents
pllx_bypass_src mux shouldn't be the parent of pllx clock
since it's only valid when when pllx BYPASS bit is set.
Thus it is actually one parent of pllx_bypass only.
Instead, pllx parent should be fixed to osc according to
reference manual.
Other plls have the same issue.
e.g. before fix, the pll tree is:
osc 6 6 24000000 0 0
pll1_bypass_src 0 0 24000000 0 0
pll1 0 0 792000000 0 0
pll1_bypass 0 0 792000000 0 0
pll1_sys 0 0 792000000 0 0
After the fix, it's:
osc 6 6 24000000 0 0
pll1 0 0 792000000 0 0
pll1_bypass 0 0 792000000 0 0
pll1_sys 0 0 792000000 0 0
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions