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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-08 17:40:20 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-17 09:46:19 +0200 |
| commit | 2dcb78d2266c0a8790cc92af3cd08dadee3d7c27 (patch) | |
| tree | 570a22394a4eecc70d722954ffcffbeb5c455b9f /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | arm64: dts: renesas: r8a779f0: Add L3 cache controller (diff) | |
| download | linux-dev-2dcb78d2266c0a8790cc92af3cd08dadee3d7c27.tar.xz linux-dev-2dcb78d2266c0a8790cc92af3cd08dadee3d7c27.zip | |
arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores
Complete the description of the Cortex-A55 CPU cores and L3 cache
controllers on the Renesas R-Car S4-8 (R8A779F0) SoC, including CPU
topology and PSCI support for enabling CPU cores.
R-Car S4-8 has 8 Cortex-A55 cores, grouped in 4 clusters.
Based on patches in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/d6af5975090d5830cb053b52400439bd1cbe8fc7.1654701480.git.geert+renesas@glider.be
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