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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-04-13 21:19:50 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-04-14 14:45:19 +0300 |
| commit | 4a0a0202b0238b652563429c5e13825ec5f83ce4 (patch) | |
| tree | 80812038e5430aed8f5c143d0bd0d693e4ef9806 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | drm/i915: Clear VLV_IIR after PIPESTAT (diff) | |
drm/i915: Clear VLV_MASTER_IER around irq processing
Like on CHV, let's clear out the master irq enable bit when we ack
GT/PM interrupts. This will allow GT/PM interrupts to re-raise the
CPU interrupt if we fail to clear all the bits from the IIR(s).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460571598-24452-5-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions