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| author |   Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp> | 2022-01-19 13:46:48 +0900 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2022-01-20 11:58:44 +0000 |
| commit | 0959bc4bd4206433ed101a1332a23e93ad16ec77 (patch) | |
| tree | 561e7358c30ab271bfc58ffcf079379fd7bf4587 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL (diff) | |
| download | linux-dev-0959bc4bd4206433ed101a1332a23e93ad16ec77.tar.xz linux-dev-0959bc4bd4206433ed101a1332a23e93ad16ec77.zip | |
net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode
Bit pattern of the ETHER_CLOCK_SEL register for RMII/MII mode should be fixed.
Also, some control bits should be modified with a specific sequence.
Fixes: b38dd98ff8d0 ("net: stmmac: Add Toshiba Visconti SoCs glue driver")
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions