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authorWen He <wen.he_1@nxp.com>2019-09-20 16:34:18 +0800
committerShawn Guo <shawnguo@kernel.org>2019-10-14 14:19:12 +0800
commit1378259773db247cd2bf754b305d463784ee707b (patch)
tree2ceb0d183d6700128e32323a662755d8340a52a7 /tools/perf/scripts/python/export-to-postgresql.py
parentarm64: dts: mark lx2160a esdhc controllers dma coherent (diff)
downloadlinux-dev-1378259773db247cd2bf754b305d463784ee707b.tar.xz
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arm64: dts: ls1028a: Update the clock providers for the Mali DP500
In order to maximise performance of the LCD Controller's 64-bit AXI bus, for any give speed bin of the device, the AXI master interface clock(ACLK) clock can be up to CPU_frequency/2, which is already capable of optimal performance. In general, ACLK is always expected to be equal to CPU_frequency/2. APB slave interface clock(PCLK) and Main processing clock(PCLK) both are tied to the same clock as ACLK. This change followed the LS1028A Architecture Specification Manual. Signed-off-by: Wen He <wen.he_1@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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