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| author |   Lucas De Marchi <lucas.demarchi@intel.com> | 2019-08-17 02:38:42 -0700 |
|---|---|---|
| committer |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-08-20 15:23:33 +0100 |
| commit | 13e53c5c533741a725cad04dfc2a5c467be60241 (patch) | |
| tree | f60f37b68f1d1bc629e660fab1c21c1d3f8d614d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/tgl: Gen12 csb support (diff) | |
| download | linux-dev-13e53c5c533741a725cad04dfc2a5c467be60241.tar.xz linux-dev-13e53c5c533741a725cad04dfc2a5c467be60241.zip | |
drm/i915/tgl: Introduce initial Tiger Lake workarounds
Add empty workaround hooks for Tiger Lake. The workarounds will be added
on separate patches. We were already applying
WaRsForcewakeAddDelayForAck, which is indeed still valid, so also update
the comment.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190817093902.2171-21-lucas.demarchi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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