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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2021-11-10 08:20:19 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-15 10:47:18 +0100 |
| commit | 161450134ae9bab3778c5f5732941162626d0eaa (patch) | |
| tree | 917ee5f5ecdeaa3c9f8e76d876d0bd0f8201b37b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros (diff) | |
| download | linux-dev-161450134ae9bab3778c5f5732941162626d0eaa.tar.xz linux-dev-161450134ae9bab3778c5f5732941162626d0eaa.zip | |
clk: renesas: r9a07g044: Add OSTM clock and reset entries
Add OSTM{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211110082019.28554-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions