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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2019-11-01 14:25:38 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-11-01 14:25:38 +0100 |
| commit | 16208387bbdd7f6503d24ee7826fbd850795a52b (patch) | |
| tree | df0053d7a3c7921b73b6771d8bc9c97b4c199b8a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | soc: renesas: Add missing check for non-zero product register address (diff) | |
| parent | dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions (diff) | |
| download | linux-dev-16208387bbdd7f6503d24ee7826fbd850795a52b.tar.xz linux-dev-16208387bbdd7f6503d24ee7826fbd850795a52b.zip | |
Merge tag 'renesas-r8a77961-dt-binding-defs-tag' into renesas-drivers-for-v5.5
Renesas R-Car M3-W+ DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions