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| author |   Phil Edworthy <phil.edworthy@renesas.com> | 2022-05-04 15:54:46 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-06 09:38:40 +0200 |
| commit | 23426d1be3c20907b4f3d72bf95234d4ee254393 (patch) | |
| tree | 2ec446e7cc89360c1d00315d51a112af86be1095 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: Add RZ/V2M support using the rzg2l driver (diff) | |
| download | linux-dev-23426d1be3c20907b4f3d72bf95234d4ee254393.tar.xz linux-dev-23426d1be3c20907b4f3d72bf95234d4ee254393.zip | |
clk: renesas: r9a09g011: Add eth clock and reset entries
Add ethernet clock/reset entries to CPG driver.
Note that the AXI and CHI clocks are both enabled and disabled using
the same register bit.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220504145454.71287-2-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions