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| author |   Gregory CLEMENT <gregory.clement@free-electrons.com> | 2015-03-17 17:33:54 +0100 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2015-03-19 11:07:47 +0100 |
| commit | 292a3546b9eb20bf5a292f4e55dd1a027424669f (patch) | |
| tree | 86a3651ede92225bbbbd6e6819263b584efde379 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: mvebu: clk: remove cpuclk resources overlapping coredivclk registers on Armada XP (diff) | |
| download | linux-dev-292a3546b9eb20bf5a292f4e55dd1a027424669f.tar.xz linux-dev-292a3546b9eb20bf5a292f4e55dd1a027424669f.zip | |
ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level
For L2 cache controller node, cache-level property is mandatory. Let's
add it to Armada 370 and Armada XP device tree.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions