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author | 2013-12-26 16:44:21 -0800 | |
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committer | 2014-02-17 16:18:02 +0200 | |
commit | 2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a (patch) | |
tree | 80532460e0a1598b4382f2e7a42287c075f758c7 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | clk: tegra: Correct clock number for UARTE (diff) | |
download | linux-dev-2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a.tar.xz linux-dev-2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a.zip |
clk: tegra: Fix PLLP rate table
This table had settings for 216MHz, but PLLP is (and is supposed to be)
configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is
not set, the kernel will panic in clk_pll_recalc_rate().
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions