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| author |   Matt Roper <matthew.d.roper@intel.com> | 2019-12-12 16:15:09 -0800 |
|---|---|---|
| committer |   Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2019-12-16 11:38:07 +0200 |
| commit | 2eeab8eb1e3a04a644cbcb8c568c26c66ea12f02 (patch) | |
| tree | c9287a953a495a80218d44992c61e8339910fba2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915: Set fence_work.ops before dma_fence_init (diff) | |
| download | linux-dev-2eeab8eb1e3a04a644cbcb8c568c26c66ea12f02.tar.xz linux-dev-2eeab8eb1e3a04a644cbcb8c568c26c66ea12f02.zip | |
drm/i915/ehl: Define EHL powerwells independently of ICL
Outputs C and D on EHL are combo PHY outputs and thus should not be
using the same TC AUX power well handlers as ICL. And even though
icl_combo_phy_aux_power_well_ops works okay for EHL/JSL combo PHYs none
of its special handling is actually necessary for this platform:
* EHL/JSL don't actually need to program PORT_CL_DW12
* Display WA #1178 does not apply to EHL/JSL
Thus we can simply drop back to using our standard "hsw-style" power
well ops for EHL AUX power wells.
Bspec: 4301
Fixes: f722b8c1e2a2 ("drm/i915/ehl: All EHL ports are combo phys")
Cc: Jose Souza <jose.souza@intel.com>
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Vivek Kasireddy <vivek.kasireddy@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191213001511.678070-2-matthew.d.roper@intel.com
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
(cherry picked from commit e8ab8d669d046a8e9b07707d2f00b9ba3e25d0ae)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions